[Drc 23-20] Rule violation (PDRC-34) MMCM_adv_ClkFrequency_div_no_dclk (Vivado 2014.2)

Question

I'm getting the following error during implementation in Vivado 2014.2. I'm using a debug hub and I set C_ENABLE_CLK_DIVIDER true in my xdc constraints. So the MMCM referred to below is the one that the Vivado tool is instantiating. This design was implementing fine for weeks then I stopped implementation before it completed. Vivado asked if I wanted to delete something (I said yes - big mistake). Ever since then, I have not been able to get it to implement.
[Drc 23-20] Rule violation (PDRC-34) MMCM_adv_ClkFrequency_div_no_dclk - The computed value 520.833 MHz (CLKIN1_PERIOD, net clk_out2) for the VCO operating frequency of the MMCME2_ADV site MMCME2_ADV_X0Y4 falls outside the operating range of the MMCM VCO frequency for this device (600 - 1440 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please adjust either the input period CLKINx_PERIOD (6.400000), multiplication factor CLKFBOUT_MULT_F (10.000000) or the division factor DIVCLK_DIVIDE (3), in order to achieve a VCO frequency within the rated operating range for this device.
Here are the constraints I entered for the debug hub
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk]

Answer 1

Yes, there are 2 other MMCM's in the design. I used the following xdc constraints to place them
set_property LOC MMCME2_ADV_X1Y7 [get_cells Core/Infra/Clks_i/MMCM_0_i/inst/mmcm_adv_inst]
set_property LOC MMCME2_ADV_X1Y6 [get_cells Core/Infra/Clks_i/MMCM_1_i/inst/mmcm_adv_inst]
The MMCM that is failing is located at MMCME2_ADV_X0Y4. This one was instantiated by the Vivado tool when I set the constraint 
set_property C_ENABLE_CLK_DIVIDER true [get_debug_cores dbg_hub]    Setting this to true causes Vivado to instantiate a MMCM inside of the debug hub. The problem appears to be that Vivado setting the parameters of the MMCM so that the output frequency is incorrect. Hence the error:
[Drc 23-20] Rule violation (PDRC-34) MMCM_adv_ClkFrequency_div_no_dclk - The computed value 520.833 MHz (CLKIN1_PERIOD, net clk_out2) for the VCO operating frequency of the MMCME2_ADV site MMCME2_ADV_X0Y4 falls outside the operating range of the MMCM VCO frequency for this device (600 - 1440 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please adjust either the input period CLKINx_PERIOD (6.400000), multiplication factor CLKFBOUT_MULT_F (10.000000) or the division factor DIVCLK_DIVIDE (3), in order to achieve a VCO frequency within the rated operating range for this device.
When set C_ENABLE_CLK_DIVIDER to false the error goes away, but the timing performance of the design is worse because the MMCM is removed. I used the MMCM here because Chipscope seems to effect the performance of my design.