Fpga debug using simulated IO via custom VI - error message

Question

I have an PXIe-7966R with MXI interface to Win7-64/LV2013-32bit. The setup is working. VI's can execute on FPGA target.
I want to debug an FPGA vi on the host computer using simulated IO via custom VI. I try to follow the tutorial in LabVIEW Help: Tutorial: Creating Test Benches (FPGA Module). Have made the custom test vi and the "inverter.vi", and set the proper simulated execution mode.
When running the "inverter.vi" (FPGA target but for now simulate on host) I get this error message dialog:
Execution already in progress
Another FPGA VI for this target is already executing on the development computer. Stop the other VI before running this vi.
I can't see where I could stop this other fpga vi. In fact I can't find this other vi at all. Here is the project, which can't be any simpler:
Any hints are welcome.
Solved!
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Answer 1

thanks for your quick reply.
I tried restart LV and sure enough this changed things. Now I get this error
which could make sense as the IO simulation VI (simTb.vi in my project) is not tested (can't do that without the fpga target under test). This is shown in part below. Note that it is the auto generated template from fpga simulation setup dialog.
and here is the fancy fpga target vi under test (yes i try to make life easy:-))
So no host vi for communication with fpga - just the simualtion test bench.
Ok, I will work on from here and try to fix the error reported. Although I dont se any reason why it reports that its not supported to write to "IO Module\TTL Out Enable 1"
But clearly a restart made a diffence.