FPGA 2010 Compilation error - TclTasklC:project_028: Unknown property value

Hi, I'm using a cRIO 9075 and a NI 9211 to measure temperature for a project busy with. Everytime I try t compile code I have a compilation error that read as follows:
Compilation failed due to a Xilinx error.
Details:
ERROR: TclTasksC: project_028:Unknown property value "spartan6" specified for "PROP_DevFamily"
Can someone help me on how to resolve this error, I'm using LabVIEW FPGA 2010 and Xilinx 11.5
Regards
Solved!
Go to Solution.

What version of the NI-RIO driver do you have?
Attached is a chart with the different compatibilities of the RIO driver.
NI-RIO and LabVIEW Version Compatibility
http://digital.ni.com/public.nsf/allkb/577CC9A7DCFC73DF8625738400116CC3?OpenDocument
Is this a 64-bit machine? Also, the minimum version of LabVIEW that will work with the 9075 is LabVIEW 2010SP1. You can verify if you have this version by going into Measurement & Austomation Explorer and expanding software. If you do not have LabVIEW 2010SP1, you will need either the platform DVDs for 2010 SP1 or you can download the content from www.NI.com/src.
You will also want to verify that you have the 2010SP1 FPGA module and 2010SP1 RT module.
Also, does this issue occur with all FPGA VIs that you try to compile or only the one that you are currently working on?
You can check by doing two things:
1. Try to compile a blank FPGA VI (i.e. nothing on the block diagram or front panel)
2. Try to compile an FPGA VI from one of the example LabVIEW projects
Please post back if one of these troubleshooting steps resolved your issue or if you're still having problems.
Jordan

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FPGA code successfully compiled in 2010 is giving compilation error in 2014.

I have developed RS485 FPGA code and successfully compiled with LabVIEW FPGA 2010.
Later changed the software to 2014 and installed Xilinx 14.7.
Now if I compile the same code with LabVIEW 2014 compile worker, i am getting error 'Process "Synthesis" failed'.
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Attached FPGA_error_2014.jpg which depicts the working and 'not working' code in 2014.
In 'Not working' code,the selector terminal is error cluster.
I am able to resolve the issue just by changing the selecter terminal to boolean as in 'working code'.
But both sets of software code works fine in version 2010.
Attachments:
FPGA_error_2014.jpg ‏128 KB

FPGA 2010 sp1 Compilation error - TclTasksC:process_077: Failed to complete.

Hi, I'm using a cRIO 9076, LabVIEW 2010 sp1, LabVIEW RT 2010 sp1, LabVIEW FPGA 2010 sp1, NI-RIO 4.0, Xilinx Compile Tools 11.5. Everytime I try to compile code I have a compilation error that read as follows (The same error come up if I try compiling a very simple VI):
Compilation failed due to a Xilinx error.
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ERROR:TclTasksCrocess_077: Failed to complete. Please inspect the log and report files.false
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Parsing package body <PkgCommIntConfiguration>.
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-->
Total memory usage is 136244 kilobytes
Number of errors   :   19 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)
Process "Synthesis" failed
Start Time: 10:15:58 a.m.
End Time: 10:16:24 a.m.
Total Time: 00:00:26,171
Can someone help me on how to resolve this error?
Regards

Hello CracKatoA
Did you make some update before this error starts to occur? Or you have never compliled any VI on this computer.
In case you have compiled any VI previously successfully on this computer, try to reinstall the LabVIEW FPGA module.
You can also try the following knowledge base:
http://digital.ni.com/public.nsf/allkb/1F8F94CF0B7D2608862577AF0072662B
Regards,
Plínio Costa
Application Engineer
National Instruments Brazil

FPGA compilation error 1026 using LV2011SP1

I just upgraded to LabVIEW 2011SP1 and I cannot get a PCI-7831R to compile. In addition to LV2011SP1, I have the following installed:
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I have a very simple VI that just has a Boolean control on the front panel sending a value to an FPGA I/O on the block diagram. I have created/compiled more complex VI's using LabVIEW 2010 without any issues. My issue with 2011SP1 is that once the intermediate files have been generated, a Code Generation Error screen pops up with Internal Errors. It says
Error 1026 occurred at an unidentified location
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I'm not sure what VI reference it is referring to. I have tried to compile this just as I have in the past, but to no avail. I have removed previous versions of LabVIEW from my machine and installed/re-installed the LabVIEW software and other modules from the distribution DVD's. It seems as though I always get into trouble when trying to upgrade the NI software.
Is there something that I am missing. I get the same message when trying to compile the examples that are included with the installs. I know that my R-Series card is installed and working properly because I can run sequences via TestStand that call VI's I created using LV2010. Any help would be appreciated!
Attachments:
ErrorWindow.jpg ‏40 KB

Hey Josh,
Thanks for responding. Late friday I added the LabVIEW real time drivers and was able to compile this once earlier this morning with no errors. I then made a small changes (by putting the Boolean control in a while loop) and tried to compile again. Now I keep getting various Xilinx compile errors. Starting to get frustrated since the errors vary slightly every time I try to compile. I will attach a couple of screen shots as well as a zip file that contains the project and VI that I am trying to compile.
Attachments:
tryout.zip ‏26 KB
Screen_Capture02 Apr. 02 12.27.jpg ‏87 KB
Screen_Capture03 Apr. 02 12.30.jpg ‏55 KB

FPGA Compile error and cannot find the compilation server

Hi,
My name is Bonghun. I recently installed the Labview 2011; previously, I installed 2010 and Labview worked very well.
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Thank you.
Attachments:
Trouble in compile.ppt ‏179 KB

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Can't Export Movie - Unknown Compile Error - Help!

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Oh, that is tragic!
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As for the Lexus, I can imagine all sorts of problems. My new LX-570 requires me to "Accept," when I put it into reverse, on the rear-view monitor! At least my wife's MB does not require that, but it is a 2011 model, so maybe the 2013 models will require that the user sign off on all sorts of "stuff."
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FPGA Compile error - Actual of formal out port cout cannot be an expression

Details:
ERROR:HDLCompiler:192 - "C:\NIFPGA\jobs\BPO5kq2_O6tyN2U\OC4_Sine_Cosine_LUT_Constant_Amplitude_dash_optimised_vi_c.vhd" Line 1408: Actual of formal out port cout cannot be an expression
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-->
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I think I know enough now to fix this problem (manually remove the path by duplicating the sub-vi) but this is perhaps a useful feedback for future bugfixes in the FPGA module. This isn't the first time this kind of incorrect code removal has given me problems but it's the first time I've been able to clearly locate the problem.
Shane
Say hello to my little friend.
RFC 2323 FHE-Compliant
Solved!
Go to Solution.

I am currently attempting a compile after changing some things.
Just a side question. Is this particular to the Reinterpret node or are other "pink nodes" also affected by this? If I don't connect the output of a high throughput add, will it result in the same behaviour?
PS OK, it seems to be compiling now. I managed to juggle around the nodes a bit in my sub-VI to make sure the "reinterpret" is not the last node before the indicator. It seems to be compiling now. A question which is in my head at this time is: Does the "reinterpret" node prevent anything before it from being optimised away by the Xilinx compiler? Are there other nodes which cannot be removed, even if the outputs are not being used? This would immediately seem to suggest to me that such nodes need to be as close to the source as possible in order to reduce the amount of code which cannot be removed as "dead code" during the Xilinx compile process.
Say hello to my little friend.
RFC 2323 FHE-Compliant

Fpga compile error Port width mismatch

When I try to compile a FPGA vi, the following error occurs.
LabVIEW FPGA: The compilation failed due to a Xilinx error.
Details:
ERROR: [Synth 8-549] port width mismatch for port 'cEIOParameter0Signal': port width = 32, actual width = 24 [C:/NIFPGA/jobs/Riuys15_TD5ekmx/NiFpgaAG_0000051e_SequenceFrame.vhd:41]
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ERROR: [Synth 8-285] failed synthesizing module 'NiFpgaAG_00000510_CaseStructureFrame_0000' [C:/NIFPGA/jobs/Riuys15_TD5ekmx/NiFpgaAG_00000510_CaseStructureFrame_0000.vhd:143]
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ERROR: [Synth 8-285] failed synthesizing module 'DM_dash_1575_ModuleResource_vi_colon_Clone19' [C:/NIFPGA/jobs/Riuys15_TD5ekmx/DM_dash_1575_ModuleResource_vi_colon_Clone19.vhd:144]
ERROR: [Synth 8-285] failed synthesizing module 'niFpgaMDKSupportARV_vi_1_colon_Clone18' [C:/NIFPGA/jobs/Riuys15_TD5ekmx/niFpgaMDKSupportARV_vi_1_colon_Clone18.vhd:143]
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ERROR: [Synth 8-285] failed synthesizing module 'TheWindow' [C:/NIFPGA/jobs/Riuys15_TD5ekmx/TheWindow.vhd:196]
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Finished RTL Elaboration : Time (s): cpu = 00:00:53 ; elapsed = 00:01:04 . Memory (MB): peak = 861.121 ; gain = 715.336
ERROR: [Common 17-39] 'source' failed due to earlier errors.
INFO: [Common 17-83] Releasing license: Synthesis
1738 Infos, 30 Warnings, 2 Critical Warnings and 14 Errors encountered.
synth_design failed
::ERROR: [Common 17-39] 'source' failed due to earlier errors.
while executing
"source -notrace {./.Xil/Vivado-9588-/realtime\toplevel_gen.tcl}"
invoked from within
"synth_design -top "toplevel_gen" -part "xc7k70tfbg676-1" -flatten_hierarchy "full""
(file "C:/NIFPGA/jobs/Riuys15_TD5ekmx/synthesize.tcl" line 25)
invoked from within
"source "C:/NIFPGA/jobs/Riuys15_TD5ekmx/synthesize.tcl""
# exit
INFO: [Common 17-206] Exiting Vivado at Thu May 07 10:24:37 2015...
I am not sure what the error is all about. Could someone help me?

It's usually better to take a look at where the code failed to compile in the process than trying to read through those logs. In future cases, you'll want to show that information as well.
Depending on your hardware, you might have been able to see the compile happen simply by hitting compile again.

Fpga DMA FIFO compilation error

Hello,
I have a cRIO 9074 with FPGA. I am trying a simple piece of code to learn how to aquire data that is generated on the FPGA at a rate of 10 KHz and transfer it to the Host VI for processing it later offline. However, I encounter this compilation error when compiling this basic FPGA VI containing a FIFO
write node (picture of the VI attached below). In the Compilation Report, it says that there were 256 Block RAMs used (the
total number is 40), therefore an error was produced. The exact compilation error
notification from the Xilinx report is reproduced below:
# Starting program map
# map -o toplevel_gen_map.ncd -intstyle xflow -timing toplevel_gen.ngd
toplevel_gen.pcf
Using target part "3s2000fg456-4".
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Running delay-based LUT packing...
ERRORack:2310 - Too many comps of type "RAMB16" found to fit
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ERROR:Map:115 - The design is too large to fit the device. Please check the Design Summary section to
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in the device. Note that the number of slices reported may not be reflected
accurately as their packing might not have been completed.
NOTE: An NCD file will still be
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Bitstream Not Created
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What does this mean? How can I fix this error?
Thank you,
Bogdan
Solved!
Go to Solution.
Attachments:
FPGA.png ‏16 KB

Sorry, I forgot to mention that...LAbVIEW 2009. And yes, this is the only loop on the FPGA.vi. I just made up this code to understand how exactly I would save some data on the host for subsequent processing, but I didn't get to that point because the VI on the FPGA does not compile successfully. Do you know of any example of the most basic code for DMA FIFOs between the FPGA and Host Computer? This should be pretty straight forward, but for some reason it's not.
Thanks,
Bogdan

Labview 2011 FPGA Compile Error

Hi,
I'm new to FPGA. I want to use Labview 2011 SP1 with the Spartan 3E starter kit from Xilinx (Spartan 3E driver available from NI labview website).
I'm trying to work my way through the examples that came with the driver. I've run into the same compiler error with a number of the examples. The error is attached.
Error 7 occurred at Read from Text File in niFpgaCompileWorker_CheckForErrors.vi->niFpgaCompileWorker_JobComplete.vi->niFpgaCompile_Worker.vi:1
Possible reason(s):
LabVIEW: File not found. The file might have been moved or deleted, or the file path might be incorrectly formatted for the operating system. For example, use \ as path separators on Windows, : on Mac OS X, and / on Linux. Verify that the path is correct using the command prompt or file explorer.
C:\NIFPGA\compilation\Shift_FPGATarget_Shift_87E8371C\Spartan3EStarter.bld
I've checked the registry to ensure that the path to the compiler is correct.
Any assistance would be welcome.
Regards,
James.
Attachments:
Labview2011_FPGA_CompileError.JPG ‏96 KB

Hi,
I don't have any Xilinx tools installed - other than the ones that installed with the Labview FPGA module.
I have attached the compilation logs and output results from my attempt.
I have renamed the extension on the following files from .lvtxt to .txt
BuildResults.txt
CodeGenerationResults.txt
Regards,
James
Attachments:
BuildResults.txt ‏5 KB
XilinxLog.txt ‏42 KB

Crio FPGA Compiling error

Hello All,
I've run into a compiling error that has me stumped. I'm using labview 8.5.1, NRIO 2.4.0, and FPGA 8.5.1 on a CRIO-9014 & 9104. When compiling the code attached I get the following error:
Analyzing generic Entity <bushold> in library <work> (Architecture <rtl>).
ERROR:Xst:807 - "C:/NIFPGA85/srvrTmp/LOCALH~1/PLANEV~1/bushold.vhd" line 1541: arguments of 'or' operator must have same lengths.
-->
Total memory usage is 546644 kilobytes
Number of errors   :    1 (   0 filtered)
Number of warnings : 540 (   0 filtered)
Number of infos    :    2 (   0 filtered)
ERROR:Xflow - Program xst returned error code 6. Aborting flow execution...
My best guess is this error has something to do with the metafiles generated by labview before final compilation into the FPGA bitstream. I've tried tweaking the code here and there and haven't found the source of the error yet. I'm going to go through with disable blocks and see where the error lies.
Anyone else run into something like this? I could use some help.
Attachments:
FPGA Code.zip ‏1354 KB

Hi mmalluck,
Clusters of 1D arrays are supported in LabVIEW FPGA. I was able to compile a small VI with code similar to yours - a for loop with four autoindexed tunnels bundled into a cluster.
I am not entirely sure why separating the arrays eliminated that error, but I am glad to hear that your program compiles now.
Jennifer R.
National Instruments
Applications Engineer

FPGA 2010 Compilation error - TclTasklC:project_028: Unknown property value

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