Help on ddr in Tux 8.1

Any help/pointers are really appreciated....
We are in the process of trying out DDR in Tux. Our version is 8.1 - 32-bit and we use view32. We have an existing server that we want to process different requests depending on data. (everything will run on the same physical server box) and in the same domain.
ubbconfig looks so:
*GROUPS
R_8411_1 LMID=srvr_1 GRPNO=310
R_8411_2 LMID=srvr_1 GRPNO=410
*SERVERS
TTR_Server SRVGRP=R_8411_1 SRVID=160 MIN=3 MAX=5
CLOPT="-A -o /usr/local/tuxedo/dev1/log/stdout -e /usr/local/tuxedo/dev1/log/stderr"
TTR_Server SRVGRP=R_8411_2 SRVID=170 MIN=3 MAX=5
CLOPT="-A -o /usr/local/tuxedo/dev1/log/stdout -e /usr/local/tuxedo/dev1/log/stderr"
*SERVICES
TTR_11D ROUTING=loc_id
*ROUTING
loc_id FIELD=loc_id
BUFTYPE="VIEW32:in_rates"
RANGES="'AAAA00' - 'MZZZZZ':R_8411_1, 'NAAA00' - 'ZZZZZZ':R_8411_2"
Everything builds and boots up just fine but when we send any message we get the following in the ULOG. Could anyone who has done this before please tell me what I am doing wrong here:
183125.srvr01!?proc.6289.1.-2: 09-03-2009: Tuxedo Version 8.1, 32-bit
183124.srvr01!?proc.6279.1.0: ttr server ready.
183124.srvr01!?proc.6279.1.0: GP_CAT:1063: ERROR: tmroute failed, could not find routing criteria of loc_id for buffer type FML32
183124.srvr01!?proc.6279.1.0: LIBTUX_CAT:4053: ERROR: Routing function failed
Thank you all,
-SRK

Hi,
We are using TUX 8.1 and i am getting the error :
LIBTUX_CAT:4053: ERROR: Routing function failed
while invoking a tpforward call.
My ubb file for the new service is below.
"NewXXInqu"
LOAD=50 PRIO=50
BUFTYPE="ALL"
ROUTING="PARTITION"
TRANTIME=90
AUTOTRAN=N
DEFAULT: LOAD=50 PRIO=50 BUFTYPE="ALL" AUTOTRAN=N
*ROUTING
"PARTITION"
FIELD="PARTITION_ID"
BUFTYPE="FML32"
RANGES="1:P1,2:P2"
Its also giving the error : GP_CAT:1064: ERROR: Routing field for 'NewXXInqu' null.
LIBTUX_CAT:1401: WARN: tpforward tpacall failure TPESYSTEM - internal system error
I have the NewXXInqu object file created,which is linked to NewXXSvr. This server NewXXSvr is up and running, and i can see that using ps -ef.
can any one please tell me what is that im missing here. What does routing field 'xx' null mean ?
Appreciate your reply,
thanks,
gopi.

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ORACLE Instance xxxx - Can not allocate log, archival required
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Thread 2 cannot allocate new log, sequence 55487
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Fri Oct 10 21:47:45 2008
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Tux Dueñas wrote:
Bueno.
A nosotros nos apasado el error de que no se puede guardar los archive logs por falta de espacio en Disco. Eso pasa cuando algun proceso genera demasiadas ransacciones que necesitan ser escritas en los logs. Por esa razon se genera mucho archive log y se llena el espacio en disco.
Borra los archivelog mas viejos, y que ya los tengas en un backup y asi no habra problema te recomiendo tener un espacio en disco minimo de 50%I hope this is what you meant,
>
We apas the error that you can not save the archive logs for lack of space on disk. That happens when any process that generates too many ransacciones need to be written in the logs. For that reason much archive log is generated and fills the space.
Removes archivelog older, and those who already have a backup and there will be no problem so I recommend you have a disk space minimum of 50%
>
This is an international forum so to spread your message as far as possible, use a more universal language, English for example can be a good choice.
Cheers
Aman....

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Try a BIOS upgrade.
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Upping to beta BIOS 1.52, 1.55, or 1.56 fixes things for me.
Maybe for the Neo2 you should try beta 1.36 or 1.37 then? Worth a try. I believe that K8N Neo BIOS 1.4 and K8N Neo2 BIOS 1.3 are total clunkers.
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I changed the voltage of my ram from 2.6 to 2.5v and that improved the stability a lot. :D
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pos data=sorry for my english

Quote from: Stu on 26-March-06, 01:48:25
how can you have a stable OC if you have memory errors?
i don´t Know but prime no errors.
Quote from: Stu on 26-March-06, 01:48:25
forget about the OC for now, and get it working properly at stock speeds, then you can worry about getting an OC right
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Quote from: memeticvirus on 14-May-06, 15:41:10
I'm having an issue with the 1.10 BIOS that is preventing me from manualy setting the timings...The problem I'm having right now is deciding what BIOS to install and where to download it. Perhaps you could help me with that?
With pleasure! I had the same problem with the v1.10 BIOS, as did another member here. I flashed BACK to the v1.0 BIOS (make sure to use the command line switched (just run the batch file)) and was able to set timings, and then I flashed directly to the 3.0A BIOS and was able to adjust timings still. See my old thread here.
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Download the 1.0 (original) and 3.0A (latest "official") BIOS images from MSI's support site.
Downloaded the DrDos BIOS flash bootable ISO CD image from bootdisk.com
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Cut Power (flipped PSU switch in back), held down the CMOS reset switch button on the mobo and the power button for 45 seconds.
Powered up, set "Optimized Defaults" and set memory voltage to 2.75v and rebooted.
Set all "normal" BIOS parameters (boot devices, et al).
Windows (x64) loaded with no issues, Everest reported timings appropriately
Did the same procedure for the 3.0A BIOS, with similar success.
You can see my post or click on the link in my sig for detailed memory reports.
Quote from: RogerP on 15-May-06, 03:04:55
Are you running just one set of TWINX2048-3200C2's?
Just one pair. I fiddled with the CR and the only result was with the single known good DIMM my latency got slightly slower (like a 5ns drop), but still no love with 2 DIMMS. I think it is just dead. But this is not my story (at least not in this thread)...this is memticvirus's story.

Corsair xmx2 ddr 667 mhz will not run on 945p-platnium help

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Is there a mix of different RAMs makers within the board?
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Compiling and installing Tux On Ice, need a little help

I have a desktop system and a netbook that I would like to have hibernating when they aren't being used. The wiki outlined roughly how to accomplish this with this page: https://wiki.archlinux.org/index.php/Tuxonice
I downloaded from the AUR the kernel26-ice 2.6.38-4 to compile and install. I managed to compile it (I think ... correctly I hope) but every time I try to get it installed with "mkinitcpio -p kernel26-ice.preset" the build fails with these errors:
[root@blackyunzi ~]# mkinitcpio -p kernel26-ice
/etc/mkinitcpio.d/kernel26-ice.preset: line 5: /etc/mkinitcpio.d/kernel26-ice.kver: No such file or directory
==> Building image from preset: 'default'
==> WARNING: No kernel version specified. Skipping image `default'
==> Building image from preset: 'fallback'
==> WARNING: No kernel version specified. Skipping image `fallback'
[root@blackyunzi ~]# cd ~heather/aur_builds/kernel26-ice/kernel26-ice/
I have tried to CD into the build directory just to make sure I was using the correct file but that has not helped. I've never compiled my own kernel before today and I'm stymied as to what I'm doing wrong. If it matters, I compiled it as a regular user in the folder where I downloaded it to. The contents of my build directory:
[heather@blackyunzi kernel26-ice]$ ls -al kernel26-ice
total 117308
drwxr-xr-x 2 heather heather 4096 Jul 27 19:52 .
drwxr-xr-x 3 heather heather 4096 Jul 27 19:08 ..
-rw-r--r-- 1 heather heather 236395 Apr 21 05:12 2.6.38.3-sched-bfs-401.patch
-rw-r--r-- 1 heather heather 125982 May 20 18:27 config
-rw-r--r-- 1 heather heather 120300 May 20 18:27 config.x86_64
-rw-r--r-- 1 heather heather 40977284 Jul 27 19:47 kernel26-ice-2.6.38-4-x86_64.pkg.tar.xz
-rw-r--r-- 1 heather heather 665 Jul 27 19:45 kernel26-ice.install
-rw-r--r-- 1 heather heather 3111082 Jul 27 20:01 kernel26-ice.preset
-rw-r--r-- 1 heather heather 74739098 Mar 14 19:40 linux-2.6.38.tar.bz2
-rw-r--r-- 1 heather heather 186457 Jun 2 19:36 patch-2.6.38.8.bz2
-rw-r--r-- 1 heather heather 12794 Jun 7 02:14 PKGBUILD
-rw-r--r-- 1 heather heather 451933 Apr 3 15:36 reiser4-for-2.6.38.patch.bz2
-rw-r--r-- 1 heather heather 129795 May 4 18:30 tuxonice-3.2-for-2.6.38.patch.bz2
[heather@blackyunzi kernel26-ice]$
The makepkg file shows that I only changed one setting, the "-j4" bit:
# /etc/makepkg.conf
# SOURCE ACQUISITION
#-- The download utilities that makepkg should use to acquire sources
# Format: 'protocol::agent'
DLAGENTS=('ftp::/usr/bin/wget -c --passive-ftp -t 3 --waitretry=3 -O %o %u'
'http::/usr/bin/wget -c -t 3 --waitretry=3 -O %o %u'
'https::/usr/bin/wget -c -t 3 --waitretry=3 --no-check-certificate -O %o %u'
'rsync::/usr/bin/rsync -z %u %o'
'scp::/usr/bin/scp -C %u %o')
# Other common tools:
# /usr/bin/snarf
# /usr/bin/lftpget -c
# /usr/bin/curl
# ARCHITECTURE, COMPILE FLAGS
CARCH="x86_64"
CHOST="x86_64-unknown-linux-gnu"
#-- Exclusive: will only run on x86_64
# -march (or -mcpu) builds exclusively for an architecture
# -mtune optimizes for an architecture, but builds for whole processor family
CFLAGS="-march=x86-64 -mtune=generic -O2 -pipe"
CXXFLAGS="-march=x86-64 -mtune=generic -O2 -pipe"
LDFLAGS="-Wl,--hash-style=gnu -Wl,--as-needed"
#-- Make Flags: change this for DistCC/SMP systems
## While using the kernel26-ice build CK recommends you ONLY compile this kernel
## with the same number as how many cpu's you have.
## quoting his example: IE you should ONLY do make -j4 on quad core, -j2 on dual core and so on.
MAKEFLAGS="-j4"
# BUILD ENVIRONMENT
# Defaults: BUILDENV=(fakeroot !distcc color !ccache check)
# A negated environment option will do the opposite of the comments below.
#-- fakeroot: Allow building packages as a non-root user
#-- distcc: Use the Distributed C/C++/ObjC compiler
#-- color: Colorize output messages
#-- ccache: Use ccache to cache compilation
#-- check: Run the check() function if present in the PKGBUILD
BUILDENV=(fakeroot !distcc color !ccache check)
#-- If using DistCC, your MAKEFLAGS will also need modification. In addition,
#-- specify a space-delimited list of hosts running in the DistCC cluster.
#DISTCC_HOSTS=""
# GLOBAL PACKAGE OPTIONS
# These are default values for the options=() settings
# Default: OPTIONS=(strip docs libtool emptydirs zipman purge)
# A negated option will do the opposite of the comments below.
#-- strip: Strip symbols from binaries/libraries
#-- docs: Save doc directories specified by DOC_DIRS
#-- libtool: Leave libtool (.la) files in packages
#-- emptydirs: Leave empty directories in packages
#-- zipman: Compress manual (man and info) pages in MAN_DIRS with gzip
#-- purge: Remove files specified by PURGE_TARGETS
OPTIONS=(strip docs libtool emptydirs zipman purge)
#-- File integrity checks to use. Valid: md5, sha1, sha256, sha384, sha512
INTEGRITY_CHECK=(md5)
#-- Options to be used when stripping binaries. See `man strip' for details.
STRIP_BINARIES="--strip-all"
#-- Options to be used when stripping shared libraries. See `man strip' for details.
STRIP_SHARED="--strip-unneeded"
#-- Options to be used when stripping static libraries. See `man strip' for details.
STRIP_STATIC="--strip-debug"
#-- Manual (man and info) directories to compress (if zipman is specified)
MAN_DIRS=({usr{,/local}{,/share},opt/*}/{man,info})
#-- Doc directories to remove (if !docs is specified)
DOC_DIRS=(usr/{,local/}{,share/}{doc,gtk-doc} opt/*/{doc,gtk-doc})
#-- Files to be removed from all packages (if purge is specified)
PURGE_TARGETS=(usr/{,share}/info/dir .packlist *.pod)
# PACKAGE OUTPUT
# Default: put built package and cached source in build directory
#-- Destination: specify a fixed directory where all packages will be placed
#PKGDEST=/home/packages
#-- Source cache: specify a fixed directory where source files will be cached
#SRCDEST=/home/sources
#-- Source packages: specify a fixed directory where all src packages will be placed
#SRCPKGDEST=/home/srcpackages
#-- Packager: name/email of the person or organization building packages
#PACKAGER="John Doe <[email protected]>"
# EXTENSION DEFAULTS
# WARNING: Do NOT modify these variables unless you know what you are
# doing.
PKGEXT='.pkg.tar.xz'
SRCEXT='.src.tar.gz'
# vim: set ft=sh ts=2 sw=2 et:
Mkinitcpio shows, after stripping out the comments:
MODULES=""
FILES=""
HOOKS="base udev autodetect usbinput pata scsi sata lvm2 filesystems consolefont"
(no compression options)
Finally, I put the kern26-ice.preset into the /etc/mkinitcpio folder and tried to install it from there but again I met failure.
Apologies for the length but I'm getting frustrated with this issue.
Last edited by MoonSwan (2011-07-28 02:40:58)

MoonSwan wrote:I have a desktop system and a netbook that I would like to have hibernating when they aren't being used. The wiki outlined roughly how to accomplish this with this page: https://wiki.archlinux.org/index.php/Tuxonice
I downloaded from the AUR the kernel26-ice 2.6.38-4 to compile and install.
Hm... netbook.
If you don't mind trying bfs and bfq too, then you could give the pf-kernel that is mentioned in the wiki too a try:
http://aur.archlinux.org/packages.php?ID=50956
It has a repository here:
[pfkernel]
Server = http://dl.dropbox.com/u/11734958/$arch
and a thread: https://bbs.archlinux.org/viewtopic.php?id=103462
I'm not quite sure how netbook performance is affected by BFS...
It has the bonus to already be based on 3.0.
Last edited by Cdh (2011-07-28 20:35:50)

Best DDR Module for MSI K7N2/K7N2G mobos...help

Hi,
i am thinking in buying new DDR modules for my PC, and not generic ones, i mean high performance, low latency, ready to overclock modules. And i was thinking in buying PC3200 or PC3500 modules.
So, could you share your experience with me about high performance (CL2) DDR modules out there and the MSI K7N2/K7N2G mobos.
Feel free to post.
Bye.

getting quality memory is a must with these new power hungry boards.
I use both Mushkin 3200 Black low latency 2x512 in 2 machines.
I also use 2x 512 XMS Corsair 3200LL and they are equal but I favor mushkin for absolutly no problems, stable, fast.
With anything you get what you pay for.

ADC DDR source synchronous timing constraints help

Hi all,
I am using a virtex 5 xc5fx200T-1ff1738 with ISE 12.4 to capture data from an ADC (KAD5512p-50 http://www.intersil.com/content/dam/Intersil/documents/kad5/kad5512p-50.pdf).
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TIMEGRP "ADC_1_DP_TIM_GRP" OFFSET = IN 1.713ns VALID 1.487ns BEFORE ADC_1_CLK_P_IN RISING;
TIMEGRP "ADC_1_DP_TIM_GRP" OFFSET = IN 1.823ns VALID 1.629ns BEFORE ADC_1_CLK_P_IN FALLING;
ADC clock period (DDR) = 2ns
ADC clk->q rising max = 0.120ns
ADC clk->q rising min = -0.260ns
ADC clk->q falling max = 0.230ns
ADC clk->q falling min = -0.160ns
The board latency of the ADC clock to the FPGA is 0.424ns.
Each ADC data pin is trace matched between N and P, but sadly not between each bit.
Bit     Delay           Clk->Data delay (0.424ns - data delay)
0        0.481ns       0.057ns
1        0.480ns       0.056ns
2        0.481ns     0.057ns
3        0.479ns     0.055ns
4        0.481ns       0.057ns
5        0.390ns      -0.034ns
6        0.480ns       0.056ns
7        0.479ns       0.055ns
8        0.430ns       0.006ns
9        0.473ns       0.049ns
10    0.481ns       0.057ns
11      0.480ns        0.056ns
Delta of the minimum and maximum clk->data board latency = ( 0.057ns - -0.034ns ) = 0.023ns    (Right?)
From this I calculate:
Rising edge offset by:
ADC clock period - clk->q falling max - max board clk->q delay
    = 2ns - 0.230ns - 0.057ns = 1.713ns
Rising edge valid time:
ADC clock period - clk->q falling max - clk->q rising min - ( Delta of the minimum and maximum clk->data board latency )
    = 2ns - 0.230ns - 0.260ns - 0.023ns = 1.487ns
Falling edge offset by:
ADC clock period - clk->q rising max - max board clk->q delay
    = 2ns - 0.120ns - 0.057ns = 1.823ns
Falling edge valid time:
ADC clock period - clk->q rising max - clk->q falling min - ( Delta of the minimum and maximum clk->data board latency )
    = 2ns - 0.120ns - 0.160ns - 0.023ns = 1.629ns
The FPGA needs a window of 1.77ns( 1.55ns setup time + 0.16ns hold time according to the data sheet DS202 v.5.4 table 93, Tpsdcm0/Tphdcm0), which I obviously do not have given these constraints. Am I calculating this wrong?
I want to use the phase shift of the DCM to move to the clock to the "data eye." Are my constraints caluclated properly?

I haven't analyzed your numbers carefully, but at first glance, this looks more or less correct. There appears to be a simple math error in calculating your data skew : (0.057ns - -0.034ns ) = 0.023ns ; it looks like you added the negative number instead of subtracting it (which makes things worse).
Thus your overall window is small - probably around 1.419ns (correcting for your error above). This is too small to capture with global clock capture using the DCM (yes, you are interpreting Tpsdcm_0/Tphdcm_0 correctly)
The only option for static capture is to use ChipSync; bring the clock in on a CCIO and use a BUFIO to capture the data. Done this way your timing is Tpscs/Tphcs, which requires a data window of only 1.370ns (leaving a whopping 49ps of margin). Of course, this is best case - if you have duty cycle errors or other board/signal integrity issues, it will come out of this margin.
There are a few things that make this better. The Tpscs/Tphcs is measured with LVCMOS25 - using LVDS will probably make it better, but we can't really quantify how much.
Also, the board delay is mostly PVT independent - you could compensate for the static error using the IDELAY. In particular you could add one tap of delay to to data bit 5, which will add approximately 78ps to that one bit - bringing it more in line with the rest. Your overall skew would the be 57-6 = 49ps, instead of 57--34 = 91ps.
To center the data eye, you would put IDELAYs on both the clock and the data. Keep the data delays as small as possible (ideally 0 on all bits except bit 5 which is 1), and then delay the IDELAY on the clock to make the data window work. You may need to adjust your OFFSET IN constraints to match the fact that you are pushing the clock forward (subtract 2ns from the OFFSET IN to indicate that the data window comes after the clock edge, not before) - thus your commands will be of the format
TIMEGRP "ADC_1_DP_TIM_GRP" OFFSET = IN <x> ns VALID <y>ns BEFORE ADC_1_CLK_P_IN RISING;
Where <x> will be a small negative number - on the order of 1.172-2.000.
However, this will all only work if the clock is on a CC pair, not a GC pair (on Virtex-5 these were different), and that all LVDS pairs are in the same I/O bank as the clock pair. If your board is already designed, then you probably can't change this.
If you can't use chip-sync (and even at that, timing is really tight), then you will have to use some sort of dynamic calibration.
Avrum

DDR 500 help

hie , how come my HyperX DDR 500 cant be detected as DDR 500 ?
in CPU-Z
only show DDR 400 only
why ?
when i set the memory frequency in the bios
it refuse to boot

PoRsChe, This is a very good question ,And I asked the Tech. Support Guy At Corsair the Same Question, and he said that all or Mostly all the 500 MHZ Modules out there are being recognized as 400,and 433 MHZ Modules, is that since there is No REAL JEDEC PC-4000 (DDR-500) Standard Yet Published, that the BIOSes for Motherboards are Recognizing them as PC-3200 or PC-3500 (DDR-400, or DDR-433) Modules ...And the reason for this is, That not every Motherboard (BIOS) Manufacturer out there except for the "Big-Four" (MSI, ASUS, ABIT, GIGABYTE), Has High-Performance BIOSes Programed to be able to even read the SPD Codes of such "High-Speed" (DDR-500) Memory, so if the Module were to be Coded in it's SPD as DDR-500 or higher those other Manufacturers BIOSes would not be able to read the SPD, therefore the PC would NOT run ..So this is the Memory Makers way (Until a JEDEC PC-4000 Standard is Created) to keep the Consumers and the other Motherboard Manufacturers (VIA, DFI SOYO TYAN,ect.ect) Happy, as the Memory will indeed work in their Boards ....I know, I am not very good at explaining these things , But I gave it a Try ...He said the a JEDEC DDR-500 Standard is due out soon......And now the Memory Makers have started Making DDR-533, and DDR-566 Modules ..So the same will hold true for those too, Until a JEDEC Standard is Created for them as well...Do you understand?........Sean REILLY875

875 and ddr settings help plz

it's about a month ago i owned my new 875 neo fis2r mobo, i upgraded the bios to the latest version 1.8.
if any can help me and give me a brief of:
1- what is the difference between a cpu p4 2.8c or 2.8?anything
2- what a cl3 differ of cl 2.5 or cl2 is it the timing of my ram
3- with my current settings i can't reach a cpu fsb more than 230x14, if i do it manually from bios, window wont log in it restart, if i do it auto from the corecenter, when it reach the 230 231 the win blue screen appear and computer restart.
4- how can i know the best timing for the best performance for my system
5- what is 1:1 or 4:5 how can i know wich one i'm running
6- all said that msi 875 p neo fis2r have no D.O.T., [/glow]i purchased one that came with a logo on the front box that said d.o.t. technology, and in my bios the is the dot presets:private captain sergent coloneil and general, so what is going?????
nb:plz i need the help i'm new to overclocking and i want to know better about how to achieve the best settings and they mean!
thanx in advance

Kevin Keenan has a good thread on overclocking.
To answer some of your questions:
1- what is the difference between a cpu p4 2.8c or 2.8?anything
There isn't a 2.8c but the 'c' is included to indicate it is a CPU with an 800 MHz front side bus (FSB). There is also a version of the 2.8 that has a 533 FSB
2- what a cl3 differ of cl 2.5 or cl2 is it the timing of my ram
Yes. See here for an explanation.
3- with my current settings i can't reach a cpu fsb more than 230x14...
This is actually pretty high for a 2.8CPU especially at 1:1 overclock. The best I can do is 220.
4- how can i know the best timing for the best performance for my system
Start with the SPD settings. Get the FSB as high as you go and remain stable and with temperatures not getting out of control. Then start tweaking your memory settings.
5- what is 1:1 or 4:5 how can i know wich one i'm running
See P4 Neo Unofficial Guide Basically, if you have an 800 FSB CPU you are running 5:4 with FSB 200 RAM 333, 1:1 with FSB 200 RAM 400 and 4:5 with FSB 200 and RAM 500.

Help! Msi Neo-fis2r and geil DDr 3200!

I can't seem to get the right ram timing... What numbers do i need for cas etc. please help!.....

Hi again,
You've said that you've set "it", but can you tell me clearly what you've set or change before saving to CMOS?
I also need you full system specs and PSU specs, please post it in the next reply, thx.
All the Best... :D!!!

Help on ddr in Tux 8.1

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