Integrating C code into labview for ARM

Hello,
I wish to use the library functions written by Luminary engineers for their cortex-m3 controllers. If i wish to use these libraries written in C language in Labview, what i should do? There are large number of labraries are available in their websites. If any one has implemented these libraries in labview please write to me.
Nabhiraj

I would also check the Using External Code in LabVIEW manual, found here
Bilal Durrani
NI
Bilal Durrani
NI

Similar Messages

Tutorial on integrating C/C++ code into LabVIEW (6.0 through 7.0)?

Where can I get a tutorial that will show me how to integrate C or C++ code into LabVIEW?

I would also check the Using External Code in LabVIEW manual, found here
Bilal Durrani
NI
Bilal Durrani
NI

LabView for ARM - MCB2300 Audio

Hi, and thanks for reading!
  My name is Chuck and I'm an undergrad ME student taking a mechatronics course. We were asked to create a proximity alarm with the MCB2300 and an IR proximity sensor. I have the entire program running correctly, but this lab has brought up a couple questions about how to better implement audio with the LabView for ARM processors.
  I understand how interrupts work, and I've seen a couple examples online of using an interrupt with a timed loop, but I believe the current version of LabView (2010) doesn't support that feature any more. I had a couple questions about how to get a feature similar to this to work with LV 2010.
  I was thinking I could have the proximity trigger enable an interrupt that I could use to generate higher quality audio than I am already making with a While - Timer loop. However, I'm not sure how to make an increment in the interrupt VI without using some form of a loop. The solution I'm thinking of at the moment is to make a For loop run once and to have an incrementing integer separate from the loop iteration (which would only go from 0 to 1) that stores its most recent value in the shift register.
  My other question is about playing a sound file through the MCB2300. I wrote a VI that reads a .wav file and writes each sample as the output needed to drive a speaker, but that decompression turns a 10KB .wav file into a 300KB text file. I also don't have a way to really load the text file onto the board. Is there any reasonable way to go about this? I found an example online that processes audio data using the MicroVision software, but I don't want to learn a new language to implement this.
  Sorry for such a long post, I just had a couple questions and was looking for some feedback. Any help would be greatly appreciated.
Thanks so much!

charlestrep91 wrote:
Hi everyone,
I just got my Labview for ARM cortex M3 evaluation kit and I can't download a simple program to the target. I'm using the Keil ULink 2 programmer and I get this error when compiling/downloading:
[4:23:16 PM] Status: Error
SWD Communication Failure
Error: Flash Download failed - Target DLL has been cancelled
Detail: [UVSC_PRJ_FLASH_DOWNLOAD, MSG: 0X100A, STATUS: Ex.] (1)
Status: FLASH download error.
I have read about this error and NI simply refers to Ulink2 user's guide which has this description for this error:
Serial Wire Debug communication is corrupted. The target SWD interface is not working properly. Mainly caused by the target: debug block not powered or clocked properly. Avoid Deep-Sleep modes while debugging. Lower the Max Clock frequency in the ULINK USB-JTAG/SWD Adapter section.
I have tried to "Lower the Max Clock frequency in the ULINK USB-JTAG/SWD Adapter section" but it didn't resolve the problem.
I have also tried to download the program using the usb port on the dev board but instead I get this error:
[4:51:22 PM] Status: ErrorUnexpected error occurred.
[Source: Target is in debug mode
Detail: [UVSC_PRJ_ADD_GROUP, MSG: 0x1002,
STATUS: 0xA] Code: 10]
What am I supposed to do with that?? I'm wondering if the dev board is defective. And this was supposed to be plug and play...
Any help is greatly appreciated!
I'll ask the obvious question, are you intending to use SWD or just download through the JTAG. Check your settings. I have not used the ARM with LV, but can you download anything using the Keil software? Give that a try. That may tell us where the problem lies. Try to duplicate your settings in LV from the Keil sw.
Reese, (former CLAD, future CLD)
Some people call me the Space Cowboy!
Some call me the gangster of love.
Some people call me MoReese!
...I'm right here baby, right here, right here, right here at home

LabVIEW for ARM 2009 Read from text file bug

Hello,
If you use the read from text file vi for reading text files from a sdcard there is a bug when you select the option "read lines"
you cannot select how many lines you want to read, it always reads the whole file, which cause a memory fault if you read big files!
I fixed this in the code (but the software doesn't recognize a EOF anymore..) in CCGByteStreamFileSupport.c
at row 709 the memory is allocated but it tries to allocate to much (since u only want to read lines).
looking at the codes it looks like it supposed to allocated 256 for a string:
Boolean bReadEntireLine = (linemode && (cnt == 0));
if(bReadEntireLine && !cnt) {
  cnt = BUFINCR;    //BUFINCR=256
but cnt is never false since if you select read lines this is the size of the file!
the variable linemode is also the size of the file.. STRANGE!
my solution:
Boolean bReadEntireLine = (linemode && (cnt > 0)); // ==
if(bReadEntireLine) {    //if(bReadEntireLine && !cnt) {
  cnt = BUFINCR;
and now the read line option does work, and reads one line until he sees CR or LF or if the count of 256 is done.
maybe the code is good but the data link of the vi's to the variables may be not, (cnt and linemode are the size of the file!)
count should be the number of lines, like chars in char mode.
linemode should be 0 or 1.
Hope someone can fix this in the new version!
greets,
Wouter
Wouter.
"LabVIEW for ARM guru and bug destroyer"

I have another solution, the EOF works with this one.
the cnt is the bytes that are not read yet, so the first time it tries to read (and allocate 4 MB).
you only want to say that if it's in line mode and cnt > 256 (BUFINCR) cnt = BUFINCR
the next time cnt is the value of the bytes that are not read yet, so the old value minus the line (until CR LF) or if cnt (256) is reached.
with this solution the program does not try to allocate the whole file but for the max of 256.
in CCGByteStreamFileSupprt.c row 705
if(linemode && (cnt>BUFINCR)){
cnt = BUFINCR;
don't use the count input when using the vi in line mode. count does not make sense, cnt will be the total file size. also the output will be an array.
linemode seems to be the value of the file size but I checked this and it is just 0 or 1, so this is good
update: damn it doesn't work!
Wouter.
"LabVIEW for ARM guru and bug destroyer"

Can I target the STM32 Primer2 hardware with LabVIEW for ARM

The STM32 Primer2 hardware looks very cool. Can LabVIEW for Arm target this hardware? From looking at the list of ARM devices supported by LabVIEW, this would appears to be a Tier 2 device (ARM Cortex-M3) with no support for TCP/IP or IO.
Can anyone tell me the feasibility or effort required to get TCP/IP, IO, and maybe even display support for this device?
Message Edited by Jim Kring on 09-11-2009 10:46 AM

Have you ever said something you wish you could take back after having time to reflect upon it? Another forum I like, http://newsbusters.org lets the author edit his posts for a short time. Maybe NI could to that and I would not be pulling out my foot so often.
Well, perhaps I was a bit more "colorful" than I meant to be. Frustration does that to me sometimes. Still the idea of a strong rope covered with disgusting risks does get the point across magnificently. I just wish I had saved it for something more suitable.
Let me think back to some of the problems I've had in which I've lost hours trying to figure out...
1. Can't use the Wait ms function. It halts the program. Express wait works fine. It was sprinkled throughout which made it hard to isolate.
2. Some sub VIs don't run unless they are checked as inline code. I don't yet understand why.
3. At the beginning of my main vi there was a small cluster in which I filled the data from an SD card file. I used a constant of the cluster on the input of the Bundle function, but because my program and variable sizes were near the max I changed a number of variable representations to save memory. ...But I didn't replace the constant. The program started exhibiting really strange behaviors. I couldn't even get a simple state machine to run. I was reduced to commenting out (disable structure) sections to find the problem before noticing the coercion dot on the input to the bundle (The dot against the red string color doesn't stand out very strongly which is why I missed it). Apparently it overwrote memory since the older cluster was significantly larger than the new.
4. Spent a lot of time trying to get the SD card to work with SPI functions. Even though I read that 2009 supported SD card file services I didn't intuitively understand how to wire up since the Open/Create/Replace function has a ref num output which actually connects to the file(use dialog) input of the read and write functions.
5. Had a problem with breakpoints and probes not working. That apparently was caused by item #3.
6. Typo bug in the Arm_irq.c file LM3Sxxxx_GPIOCAHandlerP to LM3Sxxxx_GPIOCHandlerP
Some of these are of the rope variety. A few are actual bugs. All probably could have been solved in moments had I a local guru. Anyway, I've spent hours and my hands hurt. I hope to have this little project working on the LM3s8962 today and after some hardware changes will port it over to the Primer2... Hopefully...
This forum has been a real help... especially your quick responses.
regards to all,
David

Accessing Onboard ADC with LabVIEW for ARM

I am working with the LM3S9062 Evaluation board and LabView for ARM system, and want to measure an analog voltage using the ADC, however I cannot determine which of the Digital Inputs is linked to the ADC. I need to know how the gpio mapping corresponds to the pinout of the Device. Any thoughts?

Do you mean the LM3s8962 evaluation board? If so, the pins should be labeled accordingly on the board - ADC0, ADC1, ADC2, etc.
Drop an EIO node with the same name as the pin and it should work fine from there.
Here are the schamtics : http://www.realview.com.cn/UploadFile/2008111510295067433.pdf

How to import Verilog codes into LabVIEW FPGA?

I tried to import Verilog code by instantiation followed by the instruction in http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3,
but still I can see some errors while compiling the VI file.
Simple test Verilog file is as follows:
==============================
module andtwobits (xx, yy, zz);
input xx, yy;
output reg zz;
always @(xx,yy) begin
zz <= xx & yy;
end
endmodule
==============================
and after following up the above link, we created the instantiation file as
==============================================
library ieee;
use ieee.std_logic_1164.all;
entity mainVHDL is
port(
xxin: in std_logic;
yyin: in std_logic;
zzout: out std_logic
end mainVHDL;
architecture mainVHDL1 of mainVHDL is
COMPONENT andtwobits PORT (
zz : out std_logic;
xx : in std_logic;
yy : in std_logic);
END COMPONENT;
begin
alu : andtwobits port map(
zz => zzout,
xx => xxin,
yy => yyin);
end mainVHDL1;
==============================================
Sometimes, we observe the following error when we put the indicator on the output port,
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq_ms*" TNM =
TNM_ChinchIrq_IpIrq_ms;> [Puma20Top.ucf(890)]: INST
"*ChinchLvFpgaIrq*bIpIrq_ms*" does not match any design objects.
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq*" TNM =
TNM_ChinchIrq_IpIrq;> [Puma20Top.ucf(891)]: INST "*ChinchLvFpgaIrq*bIpIrq*"
does not match any design objects.
and interestingly, if we remove the indicator from the output port, it sucessfully compiles on the LabVIEW FPGA.
Could you take a look at and please help me to import Verilog to LabVIEW FPGA?
I've followed the basic steps of instantiation on the above link, but still it won't work.
Please find the attachment for the all files.
- andtwobits.v : original Verilog file
- andtwobits.ngc: NGC file
- andtwobits.vhd: VHD file after post-translate simulation model
- mainVHDL.vhd: instantiation main file
Since there is no example file for Verilog (there is VHDL file, but not for Verilog), it is a bit hard to do the simple execution on LabVIEW FPGA even for the examples.
Thank you very much for your support, and I'm looking forward to seeing your any help/reply as soon as possible.
Bests,
Solved!
Go to Solution.
Attachments:
attach.zip ‏57 KB

Hi,
I am facing problem in creating successfully importing VHDL wrapper file for a Verilog module,into LabVIEW FPGA using CLIP Node method. Please note that:
I am working on platform SbRIO-9606.
Labiew version used is 2011 with Xilinx 12.4 compiler tools
NI RIO 4.0 is installed
Xilinx ISE version installed in PC is also 12.4 webpack ( Though I used before Xilinx 10.1 in PC for generating .ngc file for verilog code FOR SbRIO 9642 platform, but problem remains same for both versions)
Query1. Which versions of Xilinx ISE (to be installed in PC for generating .ngc file) are compatible with Labview 2011.1(with Xilinx 12.4 Compiler tools)? Can any version be used up to 12.4?
Initially I took a basic and gate verilog example to import into LabVIEW FPGA i.e. simple_and.v and its corresponding VHDL file is SimpleAnd_Wrapper.vhd
///////////////// Verilog code of “simple_and.v”//////////////////////
module simple_and(in1, in2, out1);
   input in1,in2;
   output reg out1;
   always@( in1 or in2)
   begin
      out1 <= in1 & in2;
   end
endmodule
/////////////////VHDL Wrapper file code of “SimpleAnd_Wrapper.vhd” //////////////////////
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SimpleAnd_Wrapper IS
    port (
        in1    : in std_logic;
        in2    : in std_logic;
        out1   : out std_logic
END SimpleAnd_Wrapper;
ARCHITECTURE RTL of SimpleAnd_Wrapper IS
component simple_and
   port(
         in1    : in std_logic;
         in2    : in std_logic;
         out1   : out std_logic
end component;
BEGIN
simple_and_instant: simple_and
   port map(
            in1 => in1,
            in2 => in2,
            out1 => out1
END RTL;
Documents/tutorials followed for generating VHDL Wrapper file for Verilog core are:
NI tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. Link is http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3
In this case, I did not get any vhdl file after “post-translate simulation model step” in netlist project using simple_and.ngc file previously generated through XST. Instead I got was simple_and_translate.v.
Query2. Do I hv to name tht “v” file into “simple_and.vhd”?? Anyways it did not work both ways i.e. naming it as “simple_and with a “v” or “vhd” extension. In end I copied that “simple_and.v” post translate model file, “simple_and.ngc”, and VHDL Wrapper file “SimpleAnd_Wrapper.vhd” in the respective labview project directory.
Query3. The post-translate model file can also be generated by implementing verilog simple_and.v file, so why have to generate it by making a separate netlist project using “simple_and.ngc” file? Is there any difference between these two files simple_and_translate.v generated through separate approaches as I mentioned?
2. NI tutorial “Using Verilog Modules in a Component-Level IP Design”. Link is https://decibel.ni.com/content/docs/DOC-8218.
In this case, I generated only “simple_and.ngc” file by synthesizing “simple_and.v “file using Xilinx ISE 12.4 tool. Copied that “simple_and.ngc” and “SimpleAnd_Wrapper.vhd” file in the same directory.
Query4. What is the difference between this method and the above one?
2. I followed tutorial “Importing External IP into LABVIEW FPGA” for rest steps of creating a CLIP, declaring it and passing data between CLIP and FPGA VI. Link is http://www.ni.com/white-paper/7444/en. This VI executes perfectly on FPGA for the example”simple_and.vhd” file being provided in this tutorial.
Compilation Errors Warnings received after compiling my SimpleAnd_Wrapper.vhd file
Elaborating entity <SimpleAnd_Wrapper> (architecture <RTL>) from library <work>.
WARNING:HDLCompiler:89"\NIFPGA\jobs\WcD1f16_fqu2nOv\SimpleAnd_Wrapper.vhd"    Line 35: <simple_and> remains a black-box since it has no binding entity.
2. WARNING:NgdBuild:604 - logical block 'window/theCLIPs/Component_ dash_Level _IP_ CLIP0/simple_and_instant' with type   'simple_and' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'simple_and' is not supported in target 'spartan6'.
3. ERROR:MapLib:979 - LUT6 symbol   "window/theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainInd icator/cQ_0_rstpot" (output signal=window/theVI/ Component_dash_Level _IP_bksl_out1_ ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot) has input signal "window/internal_Component_dash_Level_IP_out1" which will be trimmed. SeeSection 5 of the Map Report File for details about why the input signal willbecome undriven.
Query5. Where lays that “section5” of map report? It maybe a ridiculous question, but sorry I really can’t find it; maybe it lays in xilnx log file!
4. ERROR:MapLib:978 - LUT6 symbol "window/theVI/Component_dash_Level_IP_bksl_ out1_ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot" (output signal= window / theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainIndicator/ cQ_0_rstpot) has an equation that uses input pin I5, which no longer has a connected signal. Please ensure that all the pins used in the equation for this LUT have signals that are not trimmed (see Section 5 of the Map Report File for details on which signals were trimmed). Error found in mapping process, exiting.Errors found during the mapping phase. Please see map report file for more details. Output files will not be written.
Seeing these errors I have reached the following conclusions.
There is some problem in making that VHDL Wrapper file, LabVIEW does not recognize the Verilog component instantiated in it and treat it as unresolved black box.
Query6. Is there any step I maybe missing while making this VHDL wrapper file; in my opinion I have tried every possibility in docs/help available in NI forums?
2. Query7. Maybe it is a pure Xilinx issue i.e. some sort of library conflict as verilog module is not binding to top VHDL module as can be seen from warning HDLCompiler89. If this is the case then how to resolve that library conflict? Some hint regarding this expected issue has been given in point 7 of tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3. But nothing has been said much about resolving that issue.
3. Because of this unidentified black box, the whole design could not be mapped and hence could not be compiled.
P.S.
I have attached labview project zip folder containing simple_translate.v, simple_and_verilog.vi file,SimpleAnd_Wrapper.xml, Xilinx log file after compilation alongwith other files. Kindly analyze and help me out in resolving this basic issue.
Please note that I have made all settings regarding:
Unchecked add I/O buffers option in XST of Xilinx ISE 12.4 project
Have set “Pack I/O Registers into IOBs” to NO in XST properties of project.
Synchronization registers are also set to zero by default of all CLIP I/O terminals.
Please I need speedy help.Thanking in you in anticipation.
Attachments:
XilinxLog.txt ‏256 KB
labview project files.zip ‏51 KB

Converting HP-BASIC code into Labview or Labwindows

I need some insight on as to whether I can use all my HP-Basic code in labview or labwindows and how? Can I create dlls and call them into labview or use the code itselg in LabWindows?
Any information will be appreciated.

A very long time ago, there was a BASIC version of LabWindows. You could not convert a Rocky Mountain BASIC program directly, but it was a fairly simple fit. You could then translate that into C code automatically through LabWindows. That was one of its selling points; you didn't have to lose all of that old BASIC code. About 10 years ago, they decided to go with only a C version of LabWindows and renamed it LabWindows/CVI. This change was made because most people who were converting from BASIC to C already had and supporting two languages and a translator was very expensive (cost, memory, processing power, complexity, - expensive in every way).
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Hope that this helps,
Bob Young
Bob Young - Test Engineer - Lapsed Certified LabVIEW Developer
DISTek Integration, Inc. - NI Alliance Member
mailto:[email protected]

Translate C code into LabVIEW

Hi, I have a function in C/C++, and I am wondering how I can have it translated into LabVIEW.
Thanks,
Andrea

There are three ways to use the code in LV.
First create a DLL or .Net assembly and call it from LV.
Second use a Formula Node. You can enter your C code directly there.
Third rewrite the code in LV.
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case <value2>
break;
case <value3>
break;
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Most runtime functins are available or can be build using two or more LV function, e. g. fprintf can be created by Format Into String followed by a File Write.
If your code contains functions pointer thats no problem. VI references are function pointers. Open VI Reference creates a function pointer and Call by Reference uses it.
Since you are mentioning C++ you may need to have a look to the object oriented programming in LV.
OK, I'm the last one, but Ihe written the most text and some hints.
Waldemar
Using 7.1.1, 8.5.1, 8.6.1, 2009 on XP and RT
Don't forget to give Kudos to good answers and/or questions

How do I get my RF signals transmitted via the Bluetooth protocol into Labview for evaluation?

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uch. Thanks for all answers, contacts etc /Peter

Petter,
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Dirk

Integrating tracking codes into iweb.....

I was so successful in solving a problem I was having here last night that I thought Id throw another question out that has been baffling me, not hard to do I might add, how do you integrate tracking codes at the beginning of each page so that Google analytics for example can track the traffic on your iweb sites??
This is also a requirement if you are using some affiliate programs so it is really very important to do. Any help anyone out there can give is VERY much appreciated! This is without a doubt the best information forums I have ever read!!....Thanks again in advance for any help on this subject!!...Matt
http://www.rdeal4u.net

Google Analytics code (ga.js) required the script to be added into your page source to precisely track the page; Step 4 in the following:
http://www.google.com/support/analytics/bin/answer.py?answer=66983#0.1.1_step3
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This is true, because they don't know iweb inner working bits.
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the floating nav bar and I have urchin.js loaded from google are coded directly to the page (you need to look at Safari Activity window)
They suggested I go to www.apple.com/feedback then select the appropriate product (iweb) and seen in a message on the subject directly to the engineers.
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It's a good idea.

I seek exemple of codes in labview for programming a robot

Hello,
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Thanks

Have you tried the vi's contained in the NXT Toolkit? It has most of the NXT-G blocks, including Move and Motor.

How can I read the trace data into LabVIEW for E5071B

HI
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Many Thanks

You want to start with the driver
In case you do not know it, you can do the driver search in LabVIEW from Tools>Instrumentation>Find Instrument Drivers. You might also want to bookmark the Instrument Driver Network for information on what a driver is and how to use it.

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I've read a couple posts about using iFrames to integrate existing JSP applications into HTMLDB, but I'm wondering if it is possible to do new development with JSP's and taglib's directly in HTMLDB (i.e. within an HTML region or something like that).
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All,
I've read a couple posts about using iFrames to integrate existing JSP applications into HTMLDB, but I'm wondering if it is possible to do new development with JSP's and taglib's directly in HTMLDB (i.e. within an HTML region or something like that).
Thanks.

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I cannot get the wave Amplitude and frequency? I don't know how to use ADC !
thanks！

Do you mean the LM3s8962 evaluation board? If so, the pins should be labeled accordingly on the board - ADC0, ADC1, ADC2, etc.
Drop an EIO node with the same name as the pin and it should work fine from there.
Here are the schamtics : http://www.realview.com.cn/UploadFile/2008111510295067433.pdf

Integrating C code into labview for ARM

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