Converting HP-BASIC code into Labview or Labwindows

I need some insight on as to whether I can use all my HP-Basic code in labview or labwindows and how? Can I create dlls and call them into labview or use the code itselg in LabWindows?
Any information will be appreciated.

A very long time ago, there was a BASIC version of LabWindows. You could not convert a Rocky Mountain BASIC program directly, but it was a fairly simple fit. You could then translate that into C code automatically through LabWindows. That was one of its selling points; you didn't have to lose all of that old BASIC code. About 10 years ago, they decided to go with only a C version of LabWindows and renamed it LabWindows/CVI. This change was made because most people who were converting from BASIC to C already had and supporting two languages and a translator was very expensive (cost, memory, processing power, complexity, - expensive in every way).
If someone has an old version, you might have an upgrade path with your old code (no, I don't have any that old). Otherwise, you could build DLLs and call them with either LabVIEW or LabWindows/CVI. You could also recreate the code with the newer language.
Hope that this helps,
Bob Young
Bob Young - Test Engineer - Lapsed Certified LabVIEW Developer
DISTek Integration, Inc. - NI Alliance Member
mailto:[email protected]

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Tutorial on integrating C/C++ code into LabVIEW (6.0 through 7.0)?

Where can I get a tutorial that will show me how to integrate C or C++ code into LabVIEW?

I would also check the Using External Code in LabVIEW manual, found here
Bilal Durrani
NI
Bilal Durrani
NI

How to import Verilog codes into LabVIEW FPGA?

I tried to import Verilog code by instantiation followed by the instruction in http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3,
but still I can see some errors while compiling the VI file.
Simple test Verilog file is as follows:
==============================
module andtwobits (xx, yy, zz);
input xx, yy;
output reg zz;
always @(xx,yy) begin
zz <= xx & yy;
end
endmodule
==============================
and after following up the above link, we created the instantiation file as
==============================================
library ieee;
use ieee.std_logic_1164.all;
entity mainVHDL is
port(
xxin: in std_logic;
yyin: in std_logic;
zzout: out std_logic
end mainVHDL;
architecture mainVHDL1 of mainVHDL is
COMPONENT andtwobits PORT (
zz : out std_logic;
xx : in std_logic;
yy : in std_logic);
END COMPONENT;
begin
alu : andtwobits port map(
zz => zzout,
xx => xxin,
yy => yyin);
end mainVHDL1;
==============================================
Sometimes, we observe the following error when we put the indicator on the output port,
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq_ms*" TNM =
TNM_ChinchIrq_IpIrq_ms;> [Puma20Top.ucf(890)]: INST
"*ChinchLvFpgaIrq*bIpIrq_ms*" does not match any design objects.
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq*" TNM =
TNM_ChinchIrq_IpIrq;> [Puma20Top.ucf(891)]: INST "*ChinchLvFpgaIrq*bIpIrq*"
does not match any design objects.
and interestingly, if we remove the indicator from the output port, it sucessfully compiles on the LabVIEW FPGA.
Could you take a look at and please help me to import Verilog to LabVIEW FPGA?
I've followed the basic steps of instantiation on the above link, but still it won't work.
Please find the attachment for the all files.
- andtwobits.v : original Verilog file
- andtwobits.ngc: NGC file
- andtwobits.vhd: VHD file after post-translate simulation model
- mainVHDL.vhd: instantiation main file
Since there is no example file for Verilog (there is VHDL file, but not for Verilog), it is a bit hard to do the simple execution on LabVIEW FPGA even for the examples.
Thank you very much for your support, and I'm looking forward to seeing your any help/reply as soon as possible.
Bests,
Solved!
Go to Solution.
Attachments:
attach.zip ‏57 KB

Hi,
I am facing problem in creating successfully importing VHDL wrapper file for a Verilog module,into LabVIEW FPGA using CLIP Node method. Please note that:
I am working on platform SbRIO-9606.
Labiew version used is 2011 with Xilinx 12.4 compiler tools
NI RIO 4.0 is installed
Xilinx ISE version installed in PC is also 12.4 webpack ( Though I used before Xilinx 10.1 in PC for generating .ngc file for verilog code FOR SbRIO 9642 platform, but problem remains same for both versions)
Query1. Which versions of Xilinx ISE (to be installed in PC for generating .ngc file) are compatible with Labview 2011.1(with Xilinx 12.4 Compiler tools)? Can any version be used up to 12.4?
Initially I took a basic and gate verilog example to import into LabVIEW FPGA i.e. simple_and.v and its corresponding VHDL file is SimpleAnd_Wrapper.vhd
///////////////// Verilog code of “simple_and.v”//////////////////////
module simple_and(in1, in2, out1);
   input in1,in2;
   output reg out1;
   always@( in1 or in2)
   begin
      out1 <= in1 & in2;
   end
endmodule
/////////////////VHDL Wrapper file code of “SimpleAnd_Wrapper.vhd” //////////////////////
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SimpleAnd_Wrapper IS
    port (
        in1    : in std_logic;
        in2    : in std_logic;
        out1   : out std_logic
END SimpleAnd_Wrapper;
ARCHITECTURE RTL of SimpleAnd_Wrapper IS
component simple_and
   port(
         in1    : in std_logic;
         in2    : in std_logic;
         out1   : out std_logic
end component;
BEGIN
simple_and_instant: simple_and
   port map(
            in1 => in1,
            in2 => in2,
            out1 => out1
END RTL;
Documents/tutorials followed for generating VHDL Wrapper file for Verilog core are:
NI tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. Link is http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3
In this case, I did not get any vhdl file after “post-translate simulation model step” in netlist project using simple_and.ngc file previously generated through XST. Instead I got was simple_and_translate.v.
Query2. Do I hv to name tht “v” file into “simple_and.vhd”?? Anyways it did not work both ways i.e. naming it as “simple_and with a “v” or “vhd” extension. In end I copied that “simple_and.v” post translate model file, “simple_and.ngc”, and VHDL Wrapper file “SimpleAnd_Wrapper.vhd” in the respective labview project directory.
Query3. The post-translate model file can also be generated by implementing verilog simple_and.v file, so why have to generate it by making a separate netlist project using “simple_and.ngc” file? Is there any difference between these two files simple_and_translate.v generated through separate approaches as I mentioned?
2. NI tutorial “Using Verilog Modules in a Component-Level IP Design”. Link is https://decibel.ni.com/content/docs/DOC-8218.
In this case, I generated only “simple_and.ngc” file by synthesizing “simple_and.v “file using Xilinx ISE 12.4 tool. Copied that “simple_and.ngc” and “SimpleAnd_Wrapper.vhd” file in the same directory.
Query4. What is the difference between this method and the above one?
2. I followed tutorial “Importing External IP into LABVIEW FPGA” for rest steps of creating a CLIP, declaring it and passing data between CLIP and FPGA VI. Link is http://www.ni.com/white-paper/7444/en. This VI executes perfectly on FPGA for the example”simple_and.vhd” file being provided in this tutorial.
Compilation Errors Warnings received after compiling my SimpleAnd_Wrapper.vhd file
Elaborating entity <SimpleAnd_Wrapper> (architecture <RTL>) from library <work>.
WARNING:HDLCompiler:89"\NIFPGA\jobs\WcD1f16_fqu2nOv\SimpleAnd_Wrapper.vhd"    Line 35: <simple_and> remains a black-box since it has no binding entity.
2. WARNING:NgdBuild:604 - logical block 'window/theCLIPs/Component_ dash_Level _IP_ CLIP0/simple_and_instant' with type   'simple_and' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'simple_and' is not supported in target 'spartan6'.
3. ERROR:MapLib:979 - LUT6 symbol   "window/theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainInd icator/cQ_0_rstpot" (output signal=window/theVI/ Component_dash_Level _IP_bksl_out1_ ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot) has input signal "window/internal_Component_dash_Level_IP_out1" which will be trimmed. SeeSection 5 of the Map Report File for details about why the input signal willbecome undriven.
Query5. Where lays that “section5” of map report? It maybe a ridiculous question, but sorry I really can’t find it; maybe it lays in xilnx log file!
4. ERROR:MapLib:978 - LUT6 symbol "window/theVI/Component_dash_Level_IP_bksl_ out1_ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot" (output signal= window / theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainIndicator/ cQ_0_rstpot) has an equation that uses input pin I5, which no longer has a connected signal. Please ensure that all the pins used in the equation for this LUT have signals that are not trimmed (see Section 5 of the Map Report File for details on which signals were trimmed). Error found in mapping process, exiting.Errors found during the mapping phase. Please see map report file for more details. Output files will not be written.
Seeing these errors I have reached the following conclusions.
There is some problem in making that VHDL Wrapper file, LabVIEW does not recognize the Verilog component instantiated in it and treat it as unresolved black box.
Query6. Is there any step I maybe missing while making this VHDL wrapper file; in my opinion I have tried every possibility in docs/help available in NI forums?
2. Query7. Maybe it is a pure Xilinx issue i.e. some sort of library conflict as verilog module is not binding to top VHDL module as can be seen from warning HDLCompiler89. If this is the case then how to resolve that library conflict? Some hint regarding this expected issue has been given in point 7 of tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3. But nothing has been said much about resolving that issue.
3. Because of this unidentified black box, the whole design could not be mapped and hence could not be compiled.
P.S.
I have attached labview project zip folder containing simple_translate.v, simple_and_verilog.vi file,SimpleAnd_Wrapper.xml, Xilinx log file after compilation alongwith other files. Kindly analyze and help me out in resolving this basic issue.
Please note that I have made all settings regarding:
Unchecked add I/O buffers option in XST of Xilinx ISE 12.4 project
Have set “Pack I/O Registers into IOBs” to NO in XST properties of project.
Synchronization registers are also set to zero by default of all CLIP I/O terminals.
Please I need speedy help.Thanking in you in anticipation.
Attachments:
XilinxLog.txt ‏256 KB
labview project files.zip ‏51 KB

Translate C code into LabVIEW

Hi, I have a function in C/C++, and I am wondering how I can have it translated into LabVIEW.
Thanks,
Andrea

There are three ways to use the code in LV.
First create a DLL or .Net assembly and call it from LV.
Second use a Formula Node. You can enter your C code directly there.
Third rewrite the code in LV.
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Rewriting in LV will cost most work and you need to have a good experience in programming in C and LV.
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case <value1>
case <value2>
break;
case <value3>
break;
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Since you are mentioning C++ you may need to have a look to the object oriented programming in LV.
OK, I'm the last one, but Ihe written the most text and some hints.
Waldemar
Using 7.1.1, 8.5.1, 8.6.1, 2009 on XP and RT
Don't forget to give Kudos to good answers and/or questions

Can we convert a T-Code into WebService.

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Thanks!
Surya.

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Converting .rpt file code into Perl code

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I have some .rpt file which contains the following code to generate the report in Oracle
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.declare line_booking a12
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I need to code to create a generic parser which actually convert the above code in a .rpt file into perl code and then finally the perl code could generate the report ...
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Shelley

Is this topic is very new to all programmers????
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Integrating C code into labview for ARM

Hello,
I wish to use the library functions written by Luminary engineers for their cortex-m3 controllers. If i wish to use these libraries written in C language in Labview, what i should do? There are large number of labraries are available in their websites. If any one has implemented these libraries in labview please write to me.
Nabhiraj

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Bilal Durrani
NI
Bilal Durrani
NI

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try this
For EDI U need SEEBURGER Adapter or Conversion agent by itemfield.
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Have look
EDI Conversion
Re: Seeburger Splitter adapter!!
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Hi,
We have a PL/SQL Oracle App server application that we will support if we can convert in j2ee/java. But when i did take a look at the code, these pl/sql contains all HTML and java code inside the stored procedures.
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What you want to do might look something like this:

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Thank you very much for any help, I am very anxious to get my ad placed.

Example of the accepted code:
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<tr><td width="125"><b><font size="2" face="Verdana">Contact Name:</font></b></td><td><font face="Verdana" size="2">Patrick</font></td></tr>
You must have an old HTML editor because that isn't INLINE CSS CODE. It's deprecated HTML code. It might work OK on Craig's List... but <font> tags won't pass W3C validation in XHTML doc types.
To express what you have above using inline CSS styles without tables would like this:
<p style="font:16px Verdana, Arial, Helvetica, Sans-serif; text-align:center"><strong>Contact Name:</strong> Patrick</p>
http://www.w3schools.com/CSS/css_howto.asp
Nancy O.
Alt-Web Design & Publishing
Web | Graphics | Print | Media Specialists
www.alt-web.com/
www.twitter.com/altweb
www.alt-web.blogspot.com

I want to convert my source code in Labview 5.1 to labview 2011

HI
I want to convert a labview program which is in labview 5.1 to labview 2011 version
i am not able to open the program in the 5.1 version.
if there is no way to convert it ,then can you tell me if 5.1 version is avialable online that is compatible with the windows7 .?
thanks
Attachments:
plant.vi ‏31 KB
PID.vi ‏104 KB
integration3.vi ‏18 KB

Post your request in this Version conversion Board
The best solution is the one you find it by yourself

How to convert the following code into an applet

Please reply for me as soon as you can.
import java.io.*;
import java.awt.Frame;
import java.awt.FlowLayout;
import java.awt.Color;
import java.awt.Insets;
import java.awt.Dimension;
import java.awt.event.WindowListener;
import java.awt.event.WindowEvent;
import java.util.Enumeration;
import javax.comm.CommPort;
import javax.comm.CommPortIdentifier;
import javax.comm.SerialPort;
import javax.comm.NoSuchPortException;
import javax.comm.PortInUseException;
public class BlackBox extends Frame implements WindowListener
     static int               portNum = 0,
                         panelNum = 0,
                         rcvDelay = 0;
     static SerialPortDisplay[]     portDisp;
     static BlackBox           win;
     static boolean               threaded = true,
                         silentReceive = false,
                         modemMode = false,
                         friendly = false;
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          super("Serial Port Black Box Tester");
          addNotify();
          addWindowListener(this);
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     public void windowDeiconified(WindowEvent event)
     public void windowOpened(WindowEvent event)
     public void windowClosed(WindowEvent event)
     public void windowActivated(WindowEvent event)
     public void windowDeactivated(WindowEvent event)
     public void windowClosing(WindowEvent event)
          cleanup();
          dispose();
          System.exit(0);
     public static void main(String[] args)
          Enumeration           ports;
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          boolean               allPorts = true,
                         lineMonitor = false;
          int               idx = 0;
          win = new BlackBox();
          win.setLayout(new FlowLayout());
          win.setBackground(Color.gray);
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               if (args[idx].equals("-h"))
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                    lineMonitor = true;
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                    modemMode = true;
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                         try
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                                        + " not found!");
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                              + args[idx]);
                    printUsage();
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                    System.out.println("No comm ports found!");
                    return;
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                    portId = (CommPortIdentifier)
                                   ports.nextElement();
                    win.addPort(portId);
          if (portNum > 0)
               if (lineMonitor)
                    if (portNum >= 2)
                         portDisp[0].setLineMonitor(portDisp[1],
                                        true);
                    else
                         System.out.println("Need 2 ports for line monitor!");
                         System.exit(0);
          else
               System.out.println("No serial ports found!");
               System.exit(0);
     private void addPort(CommPortIdentifier     portId)
          * Is this a serial port?
          if (portId.getPortType()
          == CommPortIdentifier.PORT_SERIAL)
               // Is the port in use?
               if (portId.isCurrentlyOwned())
                    System.out.println("Detected "
                              + portId.getName()
                              + " in use by "
                              + portId.getCurrentOwner());
               * Open the port and add it to our GUI
               try
                    portDisp[portNum] = new
                         SerialPortDisplay(portId,
                                   threaded,
                                   friendly,
                                   silentReceive,
                                   modemMode,
                                   rcvDelay,
                                   win);
                    this.portNum++;
               catch (PortInUseException e)
                    System.out.println(portId.getName()
                              + " in use by "
                              + e.currentOwner);
     public void addPanel(SerialPortDisplay     panel)
          Dimension     dim;
          Insets          ins;
          win.add(panel);
          win.validate();
          dim = panel.getSize();
          ins = win.getInsets();
          dim.height = ((this.panelNum + 1) * (dim.height + ins.top
                    + ins.bottom)) + 10;
          dim.width = dim.width + ins.left + ins.right + 20;
          win.setSize(dim);
          win.show();
          panelNum++;
     static void printUsage()
          System.out.println("Usage: BlackBox [-h] | [-f] [-l] [-m] [-n] [-s] [-d receive_delay] [-p ports]");
          System.out.println("Where:");
          System.out.println("\t-h     this usage message");
          System.out.println("\t-f     friendly - relinquish port if requested");
          System.out.println("\t-l     run as a line monitor");
          System.out.println("\t-m     newline is \\n\\r (modem mode)");
          System.out.println("\t-n     do not use receiver threads");
          System.out.println("\t-s     don't display received data");
          System.out.println("\t-d     sleep for receive_delay msecs after each read");
          System.out.println("\t-p     list of ports to open (separated by spaces)");
          System.exit(0);
     private void cleanup()
          SerialPort     p;
          while (portNum > 0)
               portNum--;
               panelNum--;
               * Close the port
               p = portDisp[portNum].getPort();
               if (p != null)
                    System.out.println("Closing port "
                              + portNum
                              + " ("
                              + p.getName()
                              + ")");
                    portDisp[portNum].closeBBPort();
}

hi welcome to java forum,
please do one thing for me so that i can help you, can you put your code in a code tag [code ][code ] (without spaces) so that your code can be readable easily

Convert the given code into JTREE !!!

package ref;
import java.lang.reflect.*;
class Provider {
public int i=0,j=2;
private float f=3.0f;
static double d=5.8;
int a[] = new int[10];
final int g=10;
String str;
protected double y[][]=new double[5][3];
public Provider() {
protected Provider(int c) {
public final void add(float f,double d,String s) throws ClassCastException {
private int add(int a,int b) {
return j;
public double sub(int a,int b,int c,int d) {
return d;
}//end of provider class
class Requester {
public void requesttoprovide(Object o) {
Class c1;
Method method[];
Field field[];
Constructor constructor[];
try {
c1=Class.forName(o.getClass() .getName() );//return fully qualified name
method=c1.getDeclaredMethods() ;
field=c1.getDeclaredFields() ;
constructor=c1.getDeclaredConstructors() ;
for(int i=0;i<method.length ;i++) {
System.out.println(" Method # " + i + " = " + method);
System.out.println(" Method Return Type is = " + method[i].getReturnType() );
switch(method[i].getModifiers()) {
case Modifier.PUBLIC :
System.out.println(" METHOD'S MODIFIER IS = 'PUBLIC' ");
break;
case Modifier.PRIVATE :
System.out.println(" METHOD'S MODIFIER IS = 'PRIVATE' ");
break;
case Modifier.ABSTRACT :
System.out.println(" METHOD'S MODIFIER IS = 'ABSTRACT' ");
break;
case Modifier.FINAL :
System.out.println(" METHOD'S MODIFIER IS = 'FINAL' ");
break;
case Modifier.PROTECTED :
System.out.println(" METHOD'S MODIFIER IS = 'PROTECTED' ");
break;
case Modifier.STATIC :
System.out.println(" METHOD'S MODIFIER IS = 'STATIC' ");
break;
case Modifier.TRANSIENT :
System.out.println(" METHOD'S MODIFIER IS = 'TRANSIENT' ");
break;
case Modifier.VOLATILE :
System.out.println(" METHOD'S MODIFIER IS = 'VOLATILE' ");
break;
case Modifier.NATIVE :
System.out.println(" METHOD'S MODIFIER IS = 'NATIVE' ");
break;
case Modifier.SYNCHRONIZED :
System.out.println(" METHOD'S MODIFIER IS = 'SYSCHRONIZED' ");
break;
case Modifier.STRICT :
System.out.println(" METHOD'S MODIFIER IS = 'STRICT' ");
break;
default :
System.out.println(" NO MODIFIER GIVEN ");
}//end of switch
System.out.println(" Method Found in a Class Name i.e = " + method[i].getDeclaringClass() );
for(int i=0;i<field.length ;i++) {
System.out.println(" Field # " + i + " = " + field[i]);
System.out.println(" Type of Field is = " + field[i].getType()) ;
switch(field[i].getModifiers()) {
case Modifier.PUBLIC :
System.out.println(" THE MODIFIER FOR THIS FIELD IS = 'PUBLIC' ");
break;
case Modifier.PRIVATE :
System.out.println(" THE MODIFIER FOR THIS FIELD IS = 'PRIVATE' ");
break;
case Modifier.ABSTRACT :
System.out.println(" THE MODIFIER FOR THIS FIELD IS = 'ABSTRACT' ");
break;
case Modifier.FINAL :
System.out.println(" THE MODIFIER FOR THIS FIELD IS = 'FINAL' ");
break;
case Modifier.PROTECTED :
System.out.println(" THE MODIFIER FOR THIS FIELD IS = 'PROTECTED' ");
break;
case Modifier.STATIC :
System.out.println(" THE MODIFIER FOR THIS FIELD IS = 'STATIC' ");
break;
case Modifier.TRANSIENT :
System.out.println(" THE MODIFIER FOR THIS FIELD IS = 'TRANSIENT' ");
break;
case Modifier.VOLATILE :
System.out.println(" THE MODIFIER FOR THIS FIELD IS = 'VOLATILE' ");
break;
case Modifier.NATIVE :
System.out.println(" THE MODIFIER FOR THIS FIELD IS = 'NATIVE' ");
break;
case Modifier.SYNCHRONIZED :
System.out.println(" THE MODIFIER FOR THIS FIELD IS = 'SYSCHRONIZED' ");
break;
case Modifier.STRICT :
System.out.println(" THE MODIFIER FOR THIS FIELD IS = 'STRICT' ");
break;
default :
System.out.println(" NO MODIFIER GIVEN ");
}//end of switch
for(int i=0;i<constructor.length ;i++) {
System.out.println("Constructor # " + i + " = " + constructor[i]);
switch(constructor[i].getModifiers() ) {
case Modifier.PUBLIC :
System.out.println(" CONCTRUCTOR'S MODIFIER IS = 'PUBLIC' ");
break;
case Modifier.PRIVATE :
System.out.println(" CONCTRUCTOR'S MODIFIER IS = 'PRIVATE' ");
break;
case Modifier.ABSTRACT :
System.out.println(" CONCTRUCTOR'S MODIFIER IS = 'ABSTRACT' ");
break;
case Modifier.FINAL :
System.out.println(" CONCTRUCTOR'S MODIFIER IS = 'FINAL' ");
break;
case Modifier.PROTECTED :
System.out.println(" CONCTRUCTOR'S MODIFIER IS = 'PROTECTED' ");
break;
case Modifier.STATIC :
System.out.println(" CONCTRUCTOR'S MODIFIER IS = 'STATIC' ");
break;
case Modifier.TRANSIENT :
System.out.println(" CONCTRUCTOR'S MODIFIER IS = 'TRANSIENT' ");
break;
case Modifier.VOLATILE :
System.out.println(" CONCTRUCTOR'S MODIFIER IS = 'VOLATILE' ");
break;
case Modifier.NATIVE :
System.out.println(" CONCTRUCTOR'S MODIFIER IS = 'NATIVE' ");
break;
case Modifier.SYNCHRONIZED :
System.out.println(" CONCTRUCTOR'S MODIFIER IS = 'SYSCHRONIZED' ");
break;
case Modifier.STRICT :
System.out.println(" CONCTRUCTOR'S MODIFIER IS = 'STRICT' ");
break;
default :
System.out.println(" NO MODIFIER GIVEN ");
}//end of switch
//System.out.println(" " + constructor[i].getParameterTypes() );
}catch(Exception e) {
System.out.println(e.getMessage() );
public class MainClass {
public static void main(String args[]) {
Provider p=new Provider();
//Class obj=p.getClass() ;
//System.out.println(obj.getName() );
Requester req=new Requester();
req.requesttoprovide(p) ;

hi welcome to java forum,
please do one thing for me so that i can help you, can you put your code in a code tag [code ][code ] (without spaces) so that your code can be readable easily

How to convert this VB code into c#

Public Property Cell(ByVal row_index As Integer, ByVal col_index As Integer) As Object
Get
Return _excel.Cells(row_index, col_index).value
End Get
Set(ByVal value As Object)
_excel.Cells(row_index, col_index).value = value
End Set
End Property
Thanks.

If you want to have a property called Cell that returns excel's Cells collection (which is a Range) then just do this:
public Range Cells
public get
return _excel.Cells;
// Range is accessed by .Cells
// Range has an index operator [,]
// so you can access .Cells[row,col]
If you want to intercept the indexing, then you must return a object that proxies the indexing.
class MyRange
public MyRange( Range range ) { this.range = range; }
Range range;
// This just might be the syntax you're actually looking for
public object this[int row, int col]
get {
return range[row,col];
set
range[row,col] = value;
public MyRange Cells
get {
return new MyRange( _excel.Cells );

Converting HP-BASIC code into Labview or Labwindows

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