MMCM ISERDESE1 IODELAYE1 dynamic reconfiguration

Question

Hello,
Is there a way to dynamically reconfigure parameters (generics) of an MMCM, ISERDESE1, and IODELAYE1 for Virtex 6 FPGA. Meaning, there are many parameters that can be set in the HDL. If I assign a register to modify these parameters at run-time rather than at compile time, is that possible?
For example what I want to do is change the taps of IODELAYE1 of Virtex 6. There are 64 taps for input delay and output delay. I want to change the taps for input delay on the fly without having to re-compile the code over and over again.
Thanks

Answer 1

You have to read the user guides for these devices. The answer for most things is "yes", but the mechanism is pretty different for each device (and few of them are done the way you describe).
The IDELAY  and ODELAY have mechanisms for dynamically adjusting the tap settings. Depending on the architecture (V4/V5/V6/7 series, and even in its own bizarre way S6), you can increment or decrement the tap settings by one count at a time on the fly (every couple of clocks). In the later ones (including V6)  you can also force a parallel reload of the tap values by providing a 5 bit value for the tap setting. These are all documented in the I/O User Guide for your device. Also, in the V6 there are only 32 taps available (not 64, as you say in your message).  See UG361 for an entire section on the IODELAY.
For the MMCM it depends on what you want to adjust. There is a single adjustable phase shifter that can be incremented/decremented in a similar manner to the IDELAY. See the "Dynamic Phase Shift Interface" in UG362.
Other values of the MMCM can be reprogrammed, but to do that you need to use the Dynamic Reconfiguration Port (DRP) of the DCM. This requires you to implement a small controller to address the registers within the MMCM to change the values, which can be fairly complex to do. You also need to reset the MMCM after using the DRP to allow it to re-lock (so it can't be done "live").
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