PC Configuration for Fast LV FPGA Compile

What's the state-of-the-art PC for fast LV FPGA compile?
My life becomes short, when I have to wait 2 hours to compile a 90% usage 5640R VI on my Dell Dimension 2.8GHz PC. I toggled the hyper-threading on and off, it does not change too much.

The Xilinx tools do not make use of multiple processors so having hyperthreading or multiprocessor systems will not help compile faster. Although it will allow you to work on other things using the available processor while the compilation of the FPGA consumes the other processor. The best thing to have for your system is a lot of RAM. According to Xilinx you should have between 1-2 GB for the FPGA device in the PCI-5640R.
Regards,
Joseph D.

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Hi Marcel17,
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Different configurations for each channel

Hello all,
I am using Signal Express 3.0. My task is to acquire signals from 6 channels. In my signal processing I am using steps like filtering, tone extraction and data averaging.
Is it possible to configure each channel with different parameters ?? for example
for channel 1 - max 10v, min-10v , filtering lowpass 10KHz, tone extraction-5KHz
for channel 2- max 5v , min-5v , filtering highpass 30kHZ, tone extraction 35KHz
for channel 3- max 2v, min -2v, filtering lowpass 25KHz, tone extraction 20KHz
Thanks
Vaidhin.

Your success will depend upon your hardware. The biggest issue is that you want to take the data with different ranges on each channel. If your data acquisition device is simultaneously sampled, this is not a problem, since each channel will have independent amplifiers. If your data acquisition device is scanned, the range will need to change at each data point, which will require a settling time, reducing the maximum rate you can take data. If you are taking data slowly enough, and your device is fast enough, this is not a problem. You can reduce the problem by minimizing the range changes and the amount of range change in your scan order. Don't forget the finish to start transition. Let us know what you are using and the parameters you want to run with and we can offer suggestions. Please include both range and data acquisition rate for each channel.
Once you have the data, analysis can easily be done on a per channel basis, so that should not be an issue.
Good luck and let us know if you need more information.
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Muti channel configuration for the keithley 2700

I am trying to do multi chanel configuration on the Keithley 2700. I will be using hundreds of channels and would like to be to pass configuraton once and not have to individually send configuration files. As seen in the examples, I can allready read mutiple channels.
Any input would be great. Also, I will be using a combination of voltage, amps, therocouples, and resistors. Not all configurations will be the same.
Attachments:
k2700_scan.zip ‏101 KB

In response to my question, it is best to create an array of clusters that has the channel number and the measurement type and input this array into a for loop with a ke2700 set channel list and a ke 2700 configure measurement. Similarly, you can use this same method to read a channel back. I found that if performance is an issue, it is best to group the channels by what type of measurement you want to do. This way the Keithley doesn't have to continually switch measurement types.
See example below.
Attachments:
ke2700_multichannel_config_and_read.zip ‏309 KB

Xilinx version availability for labview fpga compile

While trying to compile a Labview vi for target NI PXI 7831R, at first I didn't have
any Xilinx compile so I asked my network guy to instal it. Now it complains
that it needs 10.1 when 11.5 is available. I asked him to install the 10.1 and
he did but it isn't available to the NI FPGA compile worker. How do I solve
this?
thanks

Hi DonQuixote,
You are correct in that the PXI 7831R requires Xilinx Compile Tools 10.1. This is because this card has a Vertex II chip. You can read more about Xilinx requirements here: http://ae.natinst.com/public.nsf/webPreview/A4B20D58C051DFB386257A56007BB0B2?OpenDocument .
Have you uninstalled version 11.5? What version of LabVIEW do you have? Are you recieving an error or some other message? If so, please post a screenshot.
Thanks!
Dayna P.

Why should I adopt LABVIEW FPGA as a tool for developing my FPGA projects?

Dear Friends,
Since I have started using LABVIEW FPGA, I got too many questions in my mind looking for answers!
1-      Does anybody can tell me “why should I adopt LABVIEW FPGA as a tool for developing my FPGA projects?”
I mean there are many great tools in this field (e.g. Xilinx ISE, ….); what makes LABVIEW FPGA the perfect tools that can save my time and my money?
I’m looking for a comparison can show the following points:
·         The Code size and speed optimization.
·         Developing time.
·         Compiling time.
·         Verifying time.
·         Ability to developing in future.
·         …etc.. 2-
I’ve Spartan-3E kit, I’m so glad that LABVIEW support this kit; I do enjoyed programming the kit using LABVIEW FPGA, but there are too many obstacles!
The examples come with Spartan-3E driver don't cover all peripherals on board (e.g. LAN port is not covered)! There is a declaration at NI website which is "LabVIEW FPGA drivers and examples for all on-board resources" Located at: http://digital.ni.com/express.nsf/bycode/spartan3eI don’t think that is true!
Anyway, I will try to develop examples for the unsupported peripherals, but if the Pins of these peripherals are not defined in the UCF file, the effort is worthless! The only solution in this case is to develop VHDL code in ISE and use it in Labview FPGA using HDL node!?
3-      I wonder if NI has any plan to add support for Processor setup in Labview FPGA (Like we do in EDK)?
4-      I wonder if NI has any plan to develop a driver for Virtex-5 OpenSPARC Evaluation Platform ?http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,599&Prod=XUPV5
Thnaks & regards,Walid
Solved!
Go to Solution.

Thanks for your questions and I hope I can answer them appropriately
1. LabVIEW FPGA utilizes the intuitive graphical dataflow language of LabVIEW to target FPGA technology. LabVIEW is particularly nice for FPGA programming because of its ability to represent parallelism inherent to FPGAs. It also serves as a software-like programming experience with loops and structures which has become a focus of industry lately with C-to-gates and other abstraction efforts. Here are some general comparison along the vectors you mentioned
Code Size and speed optimization - LabVIEW FPGA is a programming language. As such, one can program badly and create designs that are too big to fit on a chip and too slow to meet timing. However, there are two main programming paradigms which you can use. The normal LabVIEW dataflow programming (meaning outside a single-cycle loop) adds registers in order to enforce dataflow and synchronization in parity with the LabVIEW model of computation. As with any abstraction, this use of registers is logic necessary to enforce LabVIEW dataflow and might not be what an expert HDL programmer would create. You trade off the simplicity of LabVIEW dataflow in this case. On the other hand, when you program inside a Single-Cycle timed loop you can achieve size and speed efficiencies comparable to many VHDL implementations. We have had many users that understand that way LabVIEW is transformed to hardware and program in such a way to create very efficient and complex systems.
Development Time - Compared to VHDL many of our users get near infinite improvements in development time due to the fact that they do not know (nor do they have to know) VHDL or Verilog. Someone who knows LabVIEW can now reach the speeds and parallelism afforded by FPGAs without learning a new language. For harware engineers (that might actually have an alternative to LabVIEW) there are still extreme time saving aspects of LabVIEW including ready-made I/O interfaces, Simple FIFO DMA transfers, stichable IP blocks, and visualizable parallism. I talk to many hardware engineers that are able to drastically improve development time with LabVIEW, especially since they are more knowledgable about the target hardware.
Compilation Time - Comparable to slightly longer to due to the extra step of generating intermediate files from the LabVIEW diagram, and the increased level of hierarchy in the design to handle abstraction.
Verification Time - One of our key development initiatives moving forward is increased debugging capabilities. Today we have the abilities to functionally simulate anything included in LabVIEW FPGA, and we recently added simluation capabilities for Imported IP through the IP Integration node on NI Labs and the ability to excite your design with simulated I/O. This functional simualation is very fast and is great for verification and quick-turn design iteration. However, we still want to provide more debugging from the timing prespective with better cycle-accurate simulation. Although significantly slower than functional simulation. Cycle-accuracy give us the next level of verification before compilation. The single cycle loop running in emulation mode is cycle accurate simluation, but we want more system level simulation moving forwrad. Finally, we have worked to import things like Xilinx chipscope (soon to be on NI Labs) for on-chip debugging, which is the final step in the verification process. In terms of verification time there are aspects (like functional simulation) that are faster than traditional methods and others that are comparable, and still other that we are continuing to refine.
Ability to develop in the future - I am not sure what you mean here but we are certainly continuing to activiely develop on the RIO platform which includes FPGA as the key diffentiating technolgoy.  If you take a look at the NI Week keynote videos (ni.com/niweek) there is no doubt from both Day 1 and Day 2 that FPGA will be an important well maintained platform for many years to come.
2. Apologies for the statement in the document. The sentence should read that there are example for most board resources.
3. We do have plans to support a processor on the FPGA through LabVIEW FPGA. In fact, you will see technology on NI Labs soon that addresses this with MicroBlaze.
4. We do not currently have plans to support any other evaluation platforms. This support was created for our counterparts in the academic space to have a platform to learn the basics of digital design on a board that many schools already have in house. We are currently foccussing on rounding out more of our off-the-shelf platform with new PCI Express R Series boards, FlexRIO with new adapter modules, cRIO with new Virtex 5 backplanes, and more.
I hope this has anwered some of the questions you have.
Regards
Rick Kuhlman | LabVIEW FPGA Product Manager | National Instruments | ni.com/fpga
Check out the FPGA IPNet for browsing, downloading, and learning about LabVIEW FPGA IP Cores

Fpga compilation xilinx error 'Process "Map" failed' - 'unroutable situation'

When I try to compile a Labview fpga project on our new system, it fails with the following error summary (the full Xilinx log is attached):
LabVIEW FPGA: The compilation failed due to a xilinx error.
Details:
ERROR:LIT:536 - IBUF symbol "aUserGpio<1>_IBUF" (output
signal=aUserGpio<1>_IBUF) has the attribute IOBDELAY set to value NONE and it
is driving an IODELAY. If the IOBDELAY attribute is on the driving PAD, it
has precedence over the IBUF one. Either the constraint or the design need
modification to prevent an unroutable situation.
Errors found during logical drc.
Design Summary
Number of errors : 1
Number of warnings : 349
Process "Map" failed
Start Time: 10:31:49 AM
End Time: 10:55:32 AM
Total Time: 00:23:43
Hardware:
NI PXIe-1071 Chassis
NI PXIe-8108 Embedded controller
NI PXIe-7965R FPGA FlexRIO FPGA module
NI 5761 250 MS/s 14 bit Analog input digitizer
Installed software:
Labview 2011 version 11.0
Labview FPGA module 11.0.0
FPGA compilation tools (Xilinx12_4)
NI FlexRIO Adapter Module Support 2.2.0
NI-RIO 4.0 (FlexRIO 2.1.0)
Xilinx DRAM compilation bug fix patch from NI article id 5E4FNCDP
Xilinx clock bug fix patch from NI article id 5GFAB7DP
replaces c:\NIFPGA\programs\Xilinx11_5\ISE\xilinx\lib\nt\libPlXil_Clocks.dll; The installed version is c:\NIFPGA\programs\Xilinx12_4-> Manually copied the dll to the installed version
The Project uses the 5761 low speed clip and a DRAM FIFO.
I tried to compile it before installing any patch, after installing the DRAM patch, and after installing both patches and always got a Xilinx error after ~10 minutes compile time. The error summary shown above and the attached Xilinx log are from compiling with both patches installed.
It compiled correctly on our older system:
Hardware:
NI PXIe-1082 Chassis
NI PXIe-8133 Embedded controller
NI PXIe-7965R FPGA FlexRIO FPGA module
NI 5761 250 MS/s 14 bit Analog input digitizer
Installed software:
Labview2011version10.0.0
LabviewFPGAmodule10.0.0
FPGAcompilationtools (Xilinx11_5)
NIFlexRIOAdapterModuleSupport2.1.0
NI-RIO3.5.1 (FlexRIO1.5.0)
XilinxDRAMcompilationbugfixpatchfromNIarticleid5E4FNCDP
Any help / suggestions greatly appreciated,
Fabrizio
Attachments:
XilinxLog.txt ‏1482 KB

Hi Torpedotown,
Can you tell me what version of FlexRIO Adapter Module Support you are using?
The 5761 Low Speed CLIP has a constraint that doesn't work properly with some versions of the compilation tools. In order to solve this you should be able to upgrade to our latest version of FAM support, or go change the constraint manually.
For the latest version of FAM support, go to http://ni.com/info and enter code "famsoftware"
If you've modified constraint files before and feel comfortable doing it yourself, let me know and I can provide you with the details on how to do that.
Thanks!
National Instruments
FlexRIO & R-Series Product Support Engineer

FPGA Compiler

Hi All,
Sine Generator - R Series.lvproj is one of the examples in the Example Finder. The example is developed for PXI 7831 R Series card. But it’s mentioned that the example can run on PXI 7841 Series card also. So I created new target and devices (7841) in the PXI system and moved the Items to Move to my new target, then I run the Sine Generator (FPGA).vi but not successful. The compiler is hanging in the following window for hours.(I am using LabVIEW 2010 with xilnix 11.5 FPGA compiler)
Also I am facing the same problem when compiling the attached simple FPGA VI. This VI has only Sine Wave Generator function and I/O node.
Why I couldn't compile the attached simple VI or provided example VI. Please add your inputs/comments
Thanks in advance
Attachments:
test3.vi ‏36 KB

There's a trick here for significantly speeding up the compilation process on certain CPUs: http://forums.ni.com/t5/LabVIEW-FPGA-Idea-Exchange/Multi-core-Compiling/idc-p/2301338#M297
(It looks like your CPU is supported)
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Fpga compilation problem (generating cores)

Hello. I am working in a lab trying to compile an FPGA for the cRIO 9074 module. There are no erros when beginning the compilation, and it runs smoothly until it reaches the "generating cores" step. At this point the following message repeats itself
All runtime messages will be recorded in
C:\NIFPGA\jobs\XR923g4_G4EhsMk\coregen.log
Saved CGP file for project 'coregen'.
Resolving generics for 'ReallyLongUniqueName_ReallyLongUniqueName'...
Applying external generics to 'ReallyLongUniqueName_ReallyLongUniqueName'...
Delivering associated files for 'ReallyLongUniqueName_ReallyLongUniqueName'...
Generating implementation netlist for
'ReallyLongUniqueName_ReallyLongUniqueName'...
Running synthesis for 'ReallyLongUniqueName_ReallyLongUniqueName'
This message repeats every 5 min or so for around 29 minutes, at which point the compiler stops, presenting the following error
ERROR:sim - Cannot rename dependency database for library "mult_gen_v11_0", file
   is
   "_cg/_dbg/ReallyLongUniqueName_ReallyLongUniqueName_xsd/mult_gen_v11_0/hdpdep
   s.ref", Temporary database file
   "C:\NIFPGA\jobs\I1wyNri_G4EhsMk\core_NiLvXipFloat32Add\tmp\_cg\_dbg\ReallyLon
   gUniqueName_ReallyLongUniqueName_xsd\mult_gen_v11_0\xil_95296_48" will
   remain. System error message is: File exists
ERROR:sim - Failed executing Tcl generator.
ERROR:sim - Failed to generate 'ReallyLongUniqueName_ReallyLongUniqueName'.
   Failed executing Tcl generator.
ERROR:sim:877 - Error found during execution of IP 'Floating-point v5.0'
I have included the xilinx log. For good measure I compiled an older FPGA we have running on a different chassis and it ran just fine, so it's not a problem with xilinx (at least I don't think it is). I have spent the better part of two days wrestling with this issue and have found no viable solutions. Any and all help would be greatly appreciated. Thanks!
Cheers,
David
Attachments:
compilationfailure_log.txt ‏179 KB

Check out this document from Xilinx. It may be caused by your antivirus not allowing access to the files that Xilinx needs to overwrite while compiling.

FPGA: compilation error: size of concat operation is different than size of the target

Today I got an error, for which I couldn't find a solution.
I use the PXI-7813R FPGA, with Xilinx tools 10.1
At compilation, the error I get is:
Compilation failed due to a Xilinx error.
Details:
ERROR:HDLParsers:804 - "C:/NIFPGA/jobs/TESY1S8_X4PR8hn/NiFpgaAG_000000ce_CaseStructureFrame_0000.vhd" Line 301. Size of concat operation is different than size of the target.
ERROR:HDLParsers:804 - "C:/NIFPGA/jobs/TESY1S8_X4PR8hn/NiFpgaAG_000000ce_CaseStructureFrame_0000.vhd" Line 372. Size of concat operation is different than size of the target.
-->
Total memory usage is 185944 kilobytes
Number of errors : 2 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
Process "Synthesis" failed
Start Time: 18:25:26
End Time: 18:28:54
Total Time: 00:03:27
What can cause a concat size difference?

This is by the way the configuration:
Project: FPGAWrapperMG100125AOD.lvproj
Target: FPGA Target (RIO0, PXI-7813R)
Build Specification: fpga_integrator_AOD_random_access
Top level VI: fpga_integrator_AOD_random_access.vi
Compiling on LabVIEW FPGA Compile Cloud Service
Compilation Tool: Xilinx 10.1
Start Time: 05.07.2011 19:06:12
Run when loaded to Fpga: FALSE
Xilinx Options
Design Strategy: Custom
Synthesis Optimization Goal: Area
Synthesis Optimization Effort: Normal
Map Overall Effort Level: Default Xilinx setting
Place and Route Overall Effort Level: High
JobId: FNW72uPWorking Directory: C:\NIFPGA\compilation\FPGAWrapperMG100_FPGATarget_fpgaintegratorAO_9D5B4237
The Xilinx log is attached.
Attachments:
XilinxLog.txt ‏80 KB

Why is the FPGA compiler server so slow?

FPGA Cloud compiler is faster because NI servers are high performance, right????
Well, my Windows 7 PC is high performance, but no luck there!
Total CPU usage is never more than 25% and total memory usage (including other applications) is less than 16%.
Why does the compile server not use all available resources? has it been restricted?
How can I leverage more power from my PC?
If NI Servers can compile code quicker, there must be plausible explanation / reason?
Please advise, how to make the compile server run faster locally?
Solved!
Go to Solution.

Try this if you haven't yet:
http://forums.ni.com/t5/LabVIEW-FPGA-Idea-Exchange/Turbo-Boost-the-speed-of-FPGA-compiles-under-Wind...
In my experience, taking advantage of Intel's Turbo Boost (my PC has i5) reduced compile time from 85 minutes to 45.
I'm currently testing Cloud Compiler and it took 110 minutes. How can Cloud Compile Server be the slowest compile?

NI FPGA Compilation error

Hi ,
I am using NI Labview version 2010 SP1 ,Xilinx 11.5 compilation tool software and i need to compile the FPGA code for NI 7851r FPGA,While i start compiltaion i am getting the error ("Error:sim 433 Could not find the selected IP. I attached the snap here.Kindly help us to fix this.
Attachments:
error.jpg ‏71 KB

Hi Jaffer,
It looks like you have all the right software installed for this compilation so I dont think that is the problem. Are you compiling your own code? Could you try a blank VI or an example for the 7851r? If the examples work then please post your project zipped together so I can view what may be going wrong. If you cannot compile a blank VI then please post a MAX technical report so I can confirm that you have all the software you need installed on the system.
MAX Tech Report:
http://digital.ni.com/public.nsf/allkb/271F252B4EF0A2E0862570E70056A1E4
Patrick H | National Instruments | Software Engineer

FPGA compilation not completing.- Generating Cores

When i compile my FPGA code I get the above window and will be in the same status for more than 10 hrs and still no progress and no errors are thrown by the compiler. I have tried with different Design strategy like Balanced, minimum time etc

What version of LV? OS?
Has FPGA compilation ever worked on this computer?
For test purposes, have you tried compiling a very simple FPGA VI? Does this happen with any VI you try to compile?
Can you tell by looking at the task monitor whether the compiler is still actively doing something (consuming CPU cycles) after 10 hours?
Mike...
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Certified LabVIEW Architect
LabVIEW Champion
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How can I reduce FPGA compiler time

Hi,
I am trying to implement a PID control loop on the FPGA of a cRIO.
The VI which runs on the FPGA target takes very long to compile (1h+).
Does anyone have an idea while the compilation takes so long and how I might be able to inprove compilation time?
The program can be found in attachment.
Best regards,
Jasper
Attachments:
PID FPGA TEST.zip ‏160 KB

Hi Jasper,
FPGA's normally take a very long time to compile compared to software compilations. 1 hour sounds about right for a slightly above average sized project. Compile times of anywhere from 2-4 hours (and longer for larger devices!) are not unheard of.
Companies who are serious about FPGA compilation and rely on quick turnaround invest in servers which contain many computers to work on the compilation (this is also why when you compile, it asks you if you would like to compile on the "local sever" (your computer) or an external server).
NI also has a cloud compiler available that will let you compile your code on their servers, however you must pay for the time. I think they offer a free trial if you wanted to see how it works.
So if you seriously need quick turnaround, you must consider some serious hardware.
Otherwise, you will have to queue up multiple compilations and let them run overnight like the rest of us.
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FPGA Compile Error due to error in mapping process

Received the following error while trying to compile a FPGA VI on a PC. (Refer to attachment for details). My PC has a fresh installation of English Windows 2000 with sp4. No other software is installed except LabVIEW 8.2 & FPGA Module 8.2 & NI-RIO.
I have checked this KB and confirmed that regional settings are English. But the error still exists. I tried compiling the same VI on my laptop with Windows 2000 sp4 and it was successful. Can someone help me? Thank you very much!
FPGA Compile Error When Compiling LabVIEW FPGA VI
Error found in mapping process, exiting...
Errors found during the mapping phase. Please see map report file for more
details. Output files will not be written.
Design Summary
Number of errors : 17
Number of warnings : 8
ERROR:Xflow - Program map returned error code 2. Aborting flow execution...
Message Edited by maimai on 01-08-2007 01:00 AM
Attachments:
FPGA Compile Error.txt ‏8 KB

Hello,
The key will of course be to isolate differences between your machines.
I wonder if the following more specific language setting could be the lingering problem. LabVIEW is a non-unicode program, and there is a language setting in Windows (at least XP) specifically for non-unicode programs. Try the following (or it's Win2K equivalent) if you haven't already:
0. Open "Control Panel"
1. Open the "Regional and Language Options"
2. On the Advanced tab, choose English (United States) from the drop-down menu under the top section "Language for non-Unicode Programs"
- This language setting is different from the setting on the "Regional Options" tab.
Any other differences you can isolate would be potentially insightful - if you have the same software versions installed in the same order on both machines, we may be looking for something a bit subtle, such as the suspected language setting.
Best Regards,
JLS
Best,
JLS
Sixclear

PC Configurat​ion for Fast LV FPGA Compile

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