Enable Master AXI interface to provide address space more than 32 bit - HLS

Hello everyone,
Is there any specific syntax in HLS to anable Master AXI interface to provide address width more than 32 bit, like 33 bit to support 8G memory space addressing?
For now we can manually modify the Verilog code generated from HLS by changing the AWADDR, ARADDR and related signals from 32 to 33 bit, and make the memory space reach upto 8G.
However this maual process spent us lots of time and the code is hard to maintain expecially when the HLS design becomes more complicated.
Could anyone please help to find a way to expend the AXI address width in HLS? Thanks.

There is an option -m_axi_addr64 to enable upto 64-bit addressing for all M_AXI ports in the config_interface option.

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Enable Master AXI interface to provide address space more than 32 bit - HLS

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