Setup external clock

I just bought a GENx192 by lucid. I was having problems with the projectmix and my audio. So I went and picked up a better clock. But now Im wondering how to hook it all up. I have it hooked up I think. But do I have to set the sample rate on both the GENx and in logic or if I have it sync right should I be able to just set the GENx and Logic should change also. Thanks.
I cant remember the name of the cable that I use but its a monster cable and it is the right one thats for sure.

I have an iMac (Intel) running Tiger 10.4.11 and when I have a digital input to this Mac I can see the signal is going in on the input meter in the iMac. But the clock source "default" is greyed out. But it must be clocking to this audiio... I figure... otherwise it would not sync to it. When I remove this input I cannot select external/digital clocking. When I connect a firewire digital audio interface and select properties for it I can select clocking for it either internal or digital.
But my real problem is on a Mac Pro running Leopard 10.5.3. On this Mac it seems to me that I cannot select external or digital clocking under any conditions.
And I am wondering if a change has been from Tiger to Leopard such that there is no option to select digital/external clocking for audio. That is the crux of my question?

Similar Messages

Single Pulse Width with External Clock

I am trying to setup a 6602 counter for a single (non-buffered) pulse width measurement with an external clock. Under normal testing, the unit under test will provide the pulses, I need to measure the number of pulses during different time periods (1, 60, and 300 seconds). I want to do a pulse width measurement and I'll supply the gate signal pulse to the counter for the specific time needed.
Under normal operation, the unit under test is wired into the counter's source and the pulse is wired into the gate. For testing purposes I am using a BNC-2121. I have the counter's source wired to the Adjustable Square Wave Output and the gate wired to the Trigger output.
Here is my C++ code. I am getting a timeout error on the read and I don't know why. Any help would be appreciated.
   //Create Task
   DAQmxCreateTask( "task1", taskHandle );
   //Create Pulse Width Channel
   DAQmxCreateCIPulseWidthChan( taskHandle,             // TaskHandle
                                                   szCtrName.c_str(),     // Counter Name
                                                   "",                             // Channel Name
                                                  dMin,                          // Min Value
                                                  dMax,                         // Max Value
                                                  DAQmx_Val_Ticks,     // Units
                                                  DAQmx_Val_Rising,    // Gate Edge
                                                  "" );                            // Scale Name
   //Set the Pulse Width Terminal to the gate signal
   DAQmxSetCIPulseWidthTerm( taskHandle,     // TaskHandle
                                                 "",                       // Channel
                                                 "/CTR2/PFI38" ); // Terminal
   //Set the Timebase Src to the counter's source
   DAQmxSetCICtrTimebaseSrc( taskHandle,         // TaskHandle
                                                "",                       // Channel
                                                "/CTR2/PFI39" );   // Terminal
   //Start Task
   DAQmxStartTask( taskHandle );
//***Send pulse to gate counter***
   //Read Counter
   DAQmxReadCounterU32( taskHandle,                      // Task Handle
                                          DAQmx_Val_Auto,           // Num Samps to Read
                                          10,                          // Timeout
                                          ulBuffer,                           // Read Buffer
                                          1000,                               // Buffer Size
                                          &lSampsRead,                 // Num Samps Read
                                          NULL );                            // Reserved

I've setup a pulse width task in NI-MAX using the onboard clock and everything worked fine, so I know the hardware is working.
My unit under test is providing the pulses (from gyros) I need to measure. The pulses indicate the position of the unit so there are X, Y and Z axis gyros. I need to measure these pulses for specific periods of time (1, 60, and 300 seconds). For example during the 1 second measurement, the X and Y gyros should measure zero pulses and the Z axis should measure 515 gyros. During a 300 second measurement the X and Y gyros should measure < 60 and the Z axis should measure 30800.
So the gyro pulses are wired to the counter input and I am using a DIO channel from NI-6508 to provide the gate pulse. The gate signal will be high for either 1, 60, or 300 seconds depending on the test. The gyro pulses are essentially the external clock to the counter. I want to count the gyro pulses during the pulse of the gate (DIO).
To simplify the setup, I connected to BNC-2121 directly to the card. I have the adjustable clock output going to the counter input of ctr0 and the trigger signal going to the gate of ctr0. Once the task has been started and before the read ( I had a breakpoint set in the code), I would press the trigger button on the BNC-2121 and hold for approx. 1 second. I then execute the Read statement, and I always get a timeout. From my experience working with NI, I'm guessing I don't have a channel property set correctly, but its not obvious to me and I can't find an example to do exactly what I'm trying to do.
The CTR2 designation in the code was the object name of the card. I have two 6602 cards in my chassis. I was using ctr0 of the second counter card, so PFI38/39 was correct.
Again, any help would be appreciated.

Processor 2.6 Bus 800 shows at XP with 200 External Clock

Hi ,
I have a Pentium4 2.6MHZBus 800, 256MB DDR Bus 400, MotherBoard MSI 865PE Neo2,HD MAXTOR 80G ,VGA GeoForce 4 8X G.Ward 128MB DDR
I upgrade the bios version to the latest 1.9 the i run "LOAD HIGHST PREFORMANCE
But : at the windows XP with SP1 i found the software with read the system configuration ..reading my processor with External clock "200"
Does it show the right ?
OR should it be shown As "800"
By the way the OverClocking on the setup is disabled
Can i use overclocking here? to what range?
Advice please
Thanks in Advace

Hi Wonkanoby,
Im little bit confuse , how can I get the optimum performace of FSB 800 of my processor ? Below is my CPU-Z report and my Computer Specs
Intel P4 2.6Ghz HT @ 2.9Ghz
MSI 865PE Neo2
Geforce FX5200 128MB DDR
80Gig Seagate 7200RPM and 40 Gig Seagate 5400RPM see-through (modified)
GENERIC 256MB DDR400 memory
Pixel View TV tuner
D-Link Internal Modem
Cooler Master AERO CPU Cooler running at 3900RPM
5 X Cooler Master Fan Casing
HEC Power Supply 350Watts
3.3V = 28Amps / 5.0V = 33Amps / 12.0V = 15Amps
MSI CD-RW 52x32x52
ASUS 16X DVD
Win2000 SP3
CPU-Z Report
CPU-Z version 1.20a.
CPU(s)
Number of CPUs 2 (1 Physical)
CPU#1 APIC ID = 0
CPU Name Intel Pentium 4
Code Name Northwood
Specification Intel(R) Pentium(R) 4 CPU 2.60GHz
Family / Model / Stepping F 2 9
Extended Family / Model 0 0
Brand ID 9
Technology 0.13 µ
Supported Instructions Sets MMX, SSE, SSE2
CPU Clock Speed 2925.0 MHz
Clock multiplier x 13.0
Front Side Bus Frequency 225.0 MHz
Bus Speed 900.0 MHz
L1 Data Cache 8 KBytes, 4-way set associative, 64 Bytes line size
L1 Trace Cache 12 Kµops, 8-way set associative
L2 Cache 512 KBytes, 8-way set associative, 64 Bytes line size
L2 Speed 2925.0 MHz (Full)
L2 Location On Chip
L2 Data Prefetch Logic yes
L2 Bus Width 256 bits
CPU#2 APIC ID = 1
CPU Name Intel Pentium 4 (logical unit)
Mainboard and chipset
Motherboard manufacturer MICRO-STAR INC.
Motherboard model MS-6728, 100
BIOS vendor American Megatrends Inc.
BIOS revision V1.7
BIOS release date 10/06/2003
Chipset Intel i865P/PE/G/i848P rev. A2
Southbridge Intel 82801EB (ICH5) rev. 2
Sensor chip Winbond W83627HF
FSB Select 533 MHz
Performance Mode enabled
AGP Status enabled, rev. 3.0
AGP Data Transfert Rate 8x
AGP Side Band Addressing supported, enabled
AGP Aperture Size 128 MBytes
Memory
DRAM Type DDR-SDRAM
DRAM Size 256 MBytes
DRAM Frequency 225.0 MHz
FSB:DRAM 1:1
CAS# Latency 2.5 clocks
RAS# to CAS# 3 clocks
RAS# Precharge 3 clocks
Cycle Time (TRAS) 6 clocks
# of memory modules 1
Module 0 DDR-SDRAM PC3200 - 256 MBytes
Software
Windows version Microsoft Windows 2000 Workstation Service Pack 3 (Build 2195)

5641R External Clock

Recently we have met with an issue when using external sampling clock on 5641R. When we use 5641R Internal,everything is O.K. Signal we get is stable. But when we use External Clock (The “Clock In “ is connected to the Sine signal generated by Pxie5652,10dBm). Abnormal phenomena: The amplitude is not stable within the acquisition time. Settings: Ni 5640R configure Timebase.vi: CDC Clock Source=SMB External Ni 5640R ADC Configue NCO.vi: Previously Configured Clock Frequency= Sine signal generated by Pxie5652.
Would you please tell me how to solve it?

Hello,
I would like to ask you a few questions and suggestions about your setup.
1) You have mentioned that you are using NI 5640R Configure Timebase.VI, Using this the clock that you bring in can only be used to PLL (Reference Clock). In order to use the CLK IN as an external sample clock, you will have to program in LabVIEW FPGA, based on the help documentation below:
2) If you are programming in LabVIEW FPGA, would you mind uploading your code, so I can take a look at it?
3) What is the clock frequency, you are importing?
Best Regards,
Jignesh P
Applications Engineer

Jitter of output digital waveform with external clock

Hi,
I need to generate digital waveform with 20 bits pattern * 1000 times. Digital waveform must be sync with 1 MHz external clock.
It is not big deal.
But there is additional requirement that digital waveform has jitter < 200 ps. It can be delayed for couple ns but it must be very stable.
Can anyone point me on that parameter? Or share your expirience?
Thanks!

Hi Andrei,
Tph on figure 3 is defined as tp - 2.2ns as we discussed earlier. The data jitter, along with channel to channel skew, is already taken into account. We don't specifically spec the data jitter since we have made this calculate for you. It is safe to say that the data jitter involved in tph is less than 200 ps however this is not a standard spec we provide.
As for additional board recommendations, what is your application? The 6562 is designed for LVDS applications. The 655x series is highly recommended for high speed TTL based applications. If you reference the 655x manual you will notice similar or better specifications in regards to setup and hold times, which again already take into account data jitter and skew.
I am curious as to why you would like the specific values documented. We provide the current specifications so that you do not have to use the individual statistics to calculate numerics such as the setup and hold times. Is there something specific you are trying to do here? You mentioned a simple example earlier, what is your actual application?
Regards,
Chris Behnke
Sr. RF Engineer
High Frequency Measurements

Configure digital filter for external clock

I am trying to use a digital filter on my PXI-6602 card and I can't get it to configure for an external clock. It keeps telling me the numbers don't match up but I don't see the logic to the numbers it supports. Here is the error I got for a time base of 100 Hz and a min pulse width of 1/(100 / 2) based on the period of 2 clock cycles.
Desired Minimum Pulse Width could not be produced.
Minimum Pulse Width is affected by the Digital Filter Timebase Source and the Digital Filter Timebase Rate. To see how these two property settings can affect the Minimum Pulse Width, refer to product documentation for more details.
Property: CI.CountEdges.DigFltr.TimebaseSrc
Requested Value: /PXI1Slot2/PFI36
Property: CI.CountEdges.DigFltr.TimebaseRate
Requested Value: 100.000000
Property: CI.CountEdges.DigFltr.MinPulseWidth
Requested Value: 20.0e-3
Supported Values: 80.0e-3 to 171.798692e6
Task Name: _unnamedTask<49>
I know my math is off since the filter uses the leading edge of the pulse but 0.08 seconds is 12.5 Hz and I don't get it. Other frequencies produce different but also odd (to me) numbers.
Attached is a copy of my VI
Attachments:
External Clock for Filter.jpg ‏131 KB

Digital filtering ensures that a high pulse is high for at least a certain time (minimum pulse width) in microseconds. This is to ensure that a fluke noise signal does not count as a high pulse. It also ensures that a voltage overshoot to the high value does not register more than one high pulse as it settles in to the value.
The specifications of the digital filtering is outline on page 3-1 to 3-3 of the 660x User Manual, found here. It specifies on page 3-3 that there are five different settings for the digital filter minimum pulse width:
5 µs
1 µs
500 ns
100 ns
Or, programmable with a custom tfltrclk (period in seconds of Filter Clock). However, when using tfltrclk, minimum pulse width needs to equal to 2*tfltrclk. Your current setup has the minimum pulse width set up for minimum pulse width = 1/(tfltrclck/2) = 2/tfltrclck rather that 2*tflrclk.
I think you already knew all of this. However, the Filter Clock does not equal the Filter Clock Timebase.
If we look on page 3-3 in the manual we seed that Filter clock is actually 1/4th the speed of the Filter Clock Timebase.
Therefore, in your setup:
Filter Timebase Rate = 100Hz
Filter Clock Rate= 1/4th *100 Hz = 25Hz
Filter Clock Period = 1/25Hz = 0.04 seconds
2*Filter Clock Period = Minimum Pulse Width = 2*0.04=0.08 seconds.
Which is the minimum value it was suggesting. This will always be four times as large as what you were guessing before.
Eric S.
AE Specialist | Global Support
National Instruments

How can I use external clock to implement a delay?

Hi all,
I am testing to use external clock to drive dev/PFI0 (on device 6711) which is used as the clock for the analog ouput. I have thinking two applications by using the external clock but I don't have much idea on the implementation yet.
First of all, I have a sequence of data (array) with each sample being sent at the interval of 1us. I use an external clock (10MHz) driving the PFI0 so it is pretty easy to achieve that goal. I am thinking what happen if I want each sampel being sent at different time. For example, if I have 5 samples, I want the first one sent 1us after the task start and wait 2us to send the 2nd sample, wait 5us to send the 3rd sample and wait 11 us to send the 4th sample, and wait 1us to send the last sample. Is it possible to achieve that based on the external clock?
Second question is about the delay. My code require ciritcal timing and the builtin delay doesn't behave very well because I am running in windows. I can increase the priority of the vi to highest, it helps a bit but still not perfect. I am thinking if it is possible to implement hardward delay based on the external clock. Any idea?

Hello dragondriver,
To answer your first question, yes you could send data in that fashion. You would have to programmatically build a pulse train and use that to trigger the sending of data. The answer to the second question is essentially the same. You should be able to programmatically build a pulse train with a delay and use it as trigger to begin whatever operation you have.
Jonathan L.
Applications Engineer
National Instruments

How do I use a quadrature encoder as an external clock (PCI 6229)

Hello, ( a similar post has been placed on DAQ forum apologies as I did not know best place)
I have a PCI 6229 M Series data acquisition card. I want to use a quadrature encoder to be the external clock driving the acquisition of a number of signals. I have set up reading 24 signals each time a clock pulse is received using the DAQ assistant and set my external clock to pin pfi8 (I think) this is then connected to an encoder output. This works well enough until the encoder is run too fast when it appears I am either missing pulses or getting bounce.
How can I set up to clock using a quadrature encoder? I have seen a number of questions on this forum regarding quadrature encoders and reverse counting but not on using them as an external clock.
Basically I want to have the stability and "bounceless" nature of using two outputs from a quadrature encoder whilst still using an external clock. Is this just a case of configuring controls to certain pfi's? If so how is it done?
Any help or pointers would be helpful. So far I have managed very nicely by simply using the DAQ assistant and the interface it has would suggest that if configured for a certain pfi pin I could actually still use it.
Thanks in advance.
Kevin

Hi,
Well I've had alook into this for you and I'm not quite sure I understand what you are looking for.
Is it possible for you to phone back in to support?
The reason you are seeing bounce at high speeds, or indeed loss of points, is due to the sampling rate that you have set up.
What you will find is that the trigger will start an aquisition of a number of points at a certain rate. If your sampling rate is too low then you will not finish that sample batch before the next set of samples is recorded.
It is possible to use an external clock into a trigger or digital line, however this will limit the number of samples you can take to the speed of your encoder.
If you increase your sampling rates, and then configure a start trigger from a single input from the encoder you will be able to record a number of samples after a rising/falling edge. (Set the clock as an internal clock)
Hope this helps
AdamB
Applications Engineering Team Leader | National Instruments | UK & Ireland

Is the PXIe-PCIe8361 adequate for this system? And external clock questions...

Hi all,
I have spent some time piecing together a system and I'd like a sanity check before pulling the trigger on this purchase. The system will contain the following hardware:
1. Chassis: PXIe-1078
2. Controller: PXIe-PCIe8361
3. 3 x PXIe-6363 (16 analog inputs each card, 32 digital inputs each card, all internally clocked @ 10kHz)
4. 2 x PXI-6224 (32 digital inputs on one, 8 digital inputs on the other, externally clocked in "bursts" of 62.5khz)
5. Labview software
The three PXI-6363 cards will be responsible for a mix of analog and digital measurements made @ 10 kHz, timed continuously by the onboard clock.
One PXI-6224 will be clocked externally @ 62.5 kHz and will be used to collect digital data on a 32-bit port. These clock pulses will not be continuous, but will occur in bursts lasting for 2ms every 20ms.
The other PXI-6224 will be clocked externally @ 62.5kHz as well and will be used to collect digital data on an 8-bit port. These clock pulses will not be continuous, but will occur in bursts lasting for 2 ms at random intervals.
My questions are:
1. Am I planning anything that looks unreasonable for this hardware?
2. Should I expect issues with data transfer rates with the PXIe-PCIe8361? I will be operating well within the advertised 110MB/s throughput of the device. I plan to stream this method... NI Fast TDMS data streaming
3. I have only ever used NI cards for continuous measurements made by an onboard clock. When I set up a task to collect data that is externally-timed, will the DAQ be expecting a "continuous" clock pulse, or will the system wait patiently for clock pulses to arrive at any rate (any rate within the spec of the card, of course)?
Thanks, any input is appreciated.

Hello LucasH0011
1-As long as you put the PXI-6224 and the PXIe-6363 cards in the corresponding slots, meaning the express(PXIe-6363) in the express and the hybrid(PXI-6224) in the hybrid.
2-I think you would not have issues with the transfer rate.
3-Your timing specifications sound reasonable to me, I think you will be fine.
Here is a document that has useful concepts for the use of cards:
http://www.ni.com/white-paper/3615/en/
It is for the M-Series, but the concepts apply to the X-Series as well.
Regards
Ernesto

How to setup the clock to the second.

How to setup the clock to the second. I'm able to setup hours and minutes correctly but not the seconds precisely. Can I synchronize with an atomic clock?

Set whether iPhone sets the date and time automatically
Choose General > Date & Time and turn Set Automatically on or off.
If iPhone is set to update the time automatically, it gets the correct time over the cell network, and updates it for the time zone you're in.
from: http://support.apple.com/kb/TA38641

Is it possible to read digital data using an external clock (PCI-6259 M)?

I’m using a NI PCI-6259 M Series card and trying to write my program in VC++6.0 using the functions in the DAQmx driver.
Question1: Not all functions listed in the NI-DAQmx C Reference Help seems to be supported by my NI-card, where can I find information about which of the functions that are supported?
Question2: I want to read data from a device that clock out data on the falling edge of a clock signal. The clock signal and the data signal are routed to two DIO terminals on the NI-card. The question is if it is possible to read data using the clock as a sample clock? See two code examples below that doesn’t work. In both cases 10 samples are read at once, even if the external clock is not present.
Example 1
// Create tasks
Status = DAQmxCreateTask("", &m_ReadTrimTask);
// Set up read task
status = DAQmxCreateDIChan(m_ReadTrimTask, "Dev1/port2/line0", "", DAQmx_Val_ChanPerLine);
status = DAQmxCfgChangeDetectionTiming(m_ReadTrimTask,"Dev1/port2/line6","Dev1/port2/line6",DAQmx_Val_FiniteSamps, 10);
// Read data
int32 sampsPerChanRead, numBytesPerSamp;
status = DAQmxReadDigitalLines(m_ReadTrimTask, 10, 10.0, DAQmx_Val_GroupByChannel, result, 10, &sampsPerChanRead, &numBytesPerSamp ,NULL);
Example 2
// Create tasks
Status = DAQmxCreateTask("", &m_ReadTrimTask);
// Set up read task
status = DAQmxCreateDIChan(m_ReadTrimTask, "Dev1/port2/line0", "", DAQmx_Val_ChanPerLine);
status = DAQmxSetSampTimingType(m_ReadTrimTask, DAQmx_Val_SampClk);
status = DAQmxSetSampClkRate(m_ReadTrimTask, 1000.0);
status = DAQmxSetSampClkActiveEdge(m_ReadTrimTask, DAQmx_Val_Falling);
status = DAQmxSetSampClkSrc(m_ReadTrimTask, " Dev1/port2/line6");
// Read data
int32 sampsPerChanRead, numBytesPerSamp;
status = DAQmxReadDigitalLines(m_ReadTrimTask, 10, 10.0, DAQmx_Val_GroupByChannel, result, 10, &sampsPerChanRead, &numBytesPerSamp ,NULL);

Hello Magnus,
Thank you for contacting National Instruments.
"Question1: Not all functions listed in the NI-DAQmx C Reference Help seems to be supported by my NI-card, where can I find information about which of the functions that are supported?"
The best place to look for this information would be the M Series Help Manual. There you can find the features of your PCI-6259 and what operations it supports.
"Question2: I want to read data from a device that clock out data on the falling edge of a clock signal. The clock signal and the data signal are routed to two DIO terminals on the NI-card. The question is if it is possible to read data using the clock as a sample clock? See two code examples below that doesn’t work. In both cases 10 samples are read at once, even if the external clock is not present."
Look at the "ContReadDigChan-ExtClk_Fn.c" example project which ships with the NI-DAQ driver. This is located at: C:\Program Files\National Instruments\NI-DAQ\Examples\DAQmx ANSI C\Digital\Read Values\Cont Read Dig Chan-Ext Clk.
You will have to make some minor modifications to convert this to a finite acquisition, but that is simply a matter of changing the "sampleMode" parameter of the DAQmxCfgSampClkTiming() function. You will also have to route your clock signal to a PFI line and specify which line in your code.
I hope this helps.
Sean C.
Applications Engineering
National Instruments

Using external clock on a 6062E DAQ card

In my application I need to use an external clock (2 MHZ) to sample 10 channels at 40 KHz each. I connected the external clock to PFI_7/Startscan, enabled the ND_IN_CHANNEL_CLOCK_TIMEBASE and ND_IN_SCAN_CLOCK_TIMEBASE using The Select_signal function. If I use only two channels (instead of 10) everything works fine. If I try to increase the number of channels to more than 2 I get a digitized waveform with points missing (one every 2). I tried to decrease the sampling rate to 4 KHz per channel, but the problem persisted. For 2 channels everything is always fine, but for more than 2 I get the same error in the digitization pattern.
The relevant lines of my codes are attached
Thank you for your help
Enrico Gratt
on
Attachments:
Sample_code.pas ‏3 KB

Enrico,
I have a couple of questions. Do you see the same amount of missing data regardless of how many channels (more than 2) you are acquiring? If you use the internal 20 MHz timebase, can you successfully acquire all 10 channels at 40 kHz?
Spencer S.

Driving DO lines with external clock wired to PFI lines

Hi all,
I have few issues understanding how to use hardware timing resources in M series USB6229, with particular focus on DO. I have read last couple of day all google offered on the subject but I am still straggling with some basic tasks. To cut the story short, the 1e6 dollar question: can I set up 7 independent DO lines where (different tasks or virtual channels) where lines use same hardware timing source (eg, freqout or CO0 set to ~10kHz sampling time routed to PFI0).
Note: the reason I need 7 independent lines and not a port output (which would be obvious solution) is because I need to have (vastly) different number of samples and for each line.
Follow up question regarding timing: As I understood, any of PFI ports could be used and a input to the external clock which could be used to drive DO line(s) samples. I have tried to generate one DO, eg. P0\line4 by using CO0 to generate 10kHz sample rate. The signal on the line4 is pulse with frequency of few Hz which I routed to PF6 (with actual wire) in hope to use this signal as a clock for line5. I tried this but I am receiving errors about "resources in use"
Possible reason(s):
Specified route cannot be satisfied, because it requires resources that are currently in use by another route.
Property: SampClk.Src
Property: SampClk.ActiveEdge
Source Device: USB-6229
Source Terminal: PFI6
Required Resources in Use by
Task Name: _unnamedTask<7B>
Source Device: USB-6229
Source Terminal: PFI4
Destination Device: USB-6229
Destination Terminal: do/SampleClock
Task Name: _unnamedTask<79>
Apparently, many of internal clocks are routed internally to different PFI lines which mean the lines are occupied resource, and I do not know how to solve this.
I wanted to ask you does this principle sound as something that should work and if you know about some examples that would be excellent.
Any help would be greatly appreciated.
Cheers, Nenad

> To cut the story short, the 1e6 dollar question: can I set up 7 independent DO lines where (different tasks or virtual channels) where lines use same hardware timing source (eg, freqout or CO0 set to ~10kHz sampling time routed to PFI0).
No, you can't. The USB-6229 has a single digital output FIFO which can only be used by one task at a time.
> Note: the reason I need 7 independent lines and not a port output (which would be obvious solution) is because I need to have (vastly) different number of samples and for each line.
It should be possible to generate all seven signals with a single task by generating a waveform that includes all seven signals. If the signals repeat at different rates or you need to start/stop them independently, you will have to disable regeneration and continuously generate new waveform segments on the fly. Continuous Write Digital Port - External Clock - Non Regeneration should be a good starting point for the DAQmx programming, but actually generating the data is likely to be the challenging part.
Brad
Brad Keryan
NI R&D

NI 5772, using clk_in as an external clock

Hi.
I'm using NI 5772R with NI PXIe-7966R NI FlexRIO FPGA Module.
I'm trying to sample the signal with external clock (CLK_IN). An example file 'Clock Select (FPGA).vi' is successfully compiled. However when running 'Clock Select (host).vi', the data doesn't seem to be sampled with CLK_IN signal even if I choose the clock source as 'External Clock'. Actually externally clocked data is the same as internally clocked data.
So I wonder if this is because the signal plugged into 'CLK_IN' has wrong range. The frequency range of my CLK_IN signal is 80~160MHz, while the specification of NI5772 says the CLK_IN input range is 400-800MHz. Would it be a problem?
Also, My clock signal is sinusoidal, rather than TTL. Does the CLK_IN need to be TTL?
Thanks for your help.

Yes the output impedance of the amplifer is designed 50 ohms, so that is not an issue ...
We have hooked it up to a function generator, and gotten it to work at 500 MHz even at the lower voltages.
After unplugging the function generator, then plugging in our external clock, it will run, by the signal is corrupted at several points.
The long period duty cycle of the clock is only about 60% (i.e. there is a log period where no clock signal is sent)
I think the issue may also have to do with the clock phase, which is not unform. The NI 5772 uses a Texas Instruments ADC . Reading the manual for tha part, it seems like the clock requirements are pretty tight, as it is expecting a very low jitter clock signal
Another group we work with has a digitizer made by another company that apparently solves this issue by routing the clock though a VCO, which somehow stablizes the clock. However, after some consultation we are not convinced that is the real solution either, because the clock is supposed to be somewhat unstable in the first place, which is the issue we are trying to correct for (we are trying to avoid having to resample the data in software)

How to setup external access in VM?

We need to setup a Microsoft VM and allow external access without using my company VPN as we need to test the web services integration with other vendors. could you please help how to setup external access? Thanks

Hi Wilson,
As a prerequisite , that VM need to access the gateway .
It means that you need to
create an external virtual switch then connect that VM to external virtual switch then allocate a LAN IP for VM .
http://technet.microsoft.com/en-us/library/jj647786.aspx
After this you may think of this VM as a physical machine in your LAN then do what you need .
Best Regards
Elton Ji
We
are trying to better understand customer views on social support experience, so your participation in this
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Setup external clock

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