Zynq DMA access to PL memory (AXI BRAM)

Question

Hi,
We need to transfer data from Zynq PL memory (AXI BRAM) to DDR and also DDR to PL. We have instantiated AXI BRAM controller in PL and are using M_AXI_GP0 interface from PS. We have verified the data transfer between DDR and PL using memcpy function in the custom driver. In order to get better throughput we want to make use of Zynq DMAC. We have been able to program the DMAC to transfer data between DDR to DDR, DDR to PL and PL to DDR. We found that pl330 implementation for data transfer in case of unaligned source and destination address was incorrect. We have made the necessary changes for it and have validated this in the DDR to DDR transfers. We are facing 2 issues currently:
1. Sometimes transfer of size equal to multiple of 128 and greater than 1024 bytes (ex: 1024, 1152, etc) does not happen correctly. In such cases we have observed that a complete burst of data (i.e. 128 bytes) is not transferred at the end. This does not always happen and sometimes multiple bursts are missed. This issue is observed for data transfer from DDR to DDR, DDR to PL and also PL to DDR. 
2. In case of unaligned source and destination addresses the data last few bytes are not transferred to the destination address. This is observed only in case of DDR to PL and PL to DDR transfers and not in case of DDR to DDR transfer.
In both the above cases we have verified the source and destination addresses, SAR0 and DAR0 to be incremented correctly to the last addresses. 
Any help would be appreciated.
Regards,
Pooja

Answer 1

After fighting with it for a while it seems that flushing and invalidating the cached areas can fix it.  In my particular build it was not sufficient to do this at the start it was also needed after the done ISR fired.  Turning off caching makes the problem go completely away, but the Zynq runs terrible slow with caching off so that's not an option.  After researching this some more online... It appears the best practive for using the PS DMA is to only interact with non-cached memory areas - and aligned to 32 bytes.  In the xilinx standalone bsp there is a bunch of gotcha notes under the InvalidateRange function about all the problems with invalidating cache and flushing it that can bite.  There is a linux driver for zynq PL330 DMA, in the course of reading about it there is a PDF available online that talks about how the driver works.  The linux driver allocates uncached memory only when using the PL330 DMA.  Sounds like that's the way to go to avoid problems with DMA coherency.
Also, when building SDK example projects and selecting peripheral tests, the project will include tests for the DMA PS peripheral including testing all 8 channels of the first DMA peripheral instance in the processor system.  It's a good starting point to build from when making your own interface to the DMA using the Xilinx bare metal drivers.
Hope this helps someone out,
I struggled with this stuff for a while myself...  chasing my tail.