CFolder feasibility check
Hi ALL,
Would like to know, whether vendor can do an online PPAP submission using a cfolder. Can cfolder be integrated between ECC, SRM and DMS (document management).
Scenario is for all new products, supplier have to submit PPAP documents by online through a portal . And question here is how feasible is using cfolder.
Does cfolder requires another license to use SAP Application Server or it is coming free with any of these components, SAP ECC or SRM.
Any suggestions and recommendations regarding this topic will be very appreciable
Jason
Hi Jaison,
same as in your other thread - very straightforward and standard scenario you are talking about. And there is no additional license fee for cFolders on top of ERP/SRM, besides the users that need to be licensed (external supplier users, internal users if not covered by ERP user licenses already).
If you need more infos on cFolders for supplier collaboration scenarios, you can also reach out to me via mail through ulf dot petzel at sap dot com.
Regards, Ulf.
Similar Messages
-
Inserting new line item in Sales order
Hi,
We are doing a feasibility check to find out whether a new line item can be successfully inserted into a sales order based on certain pricing conditions that is received through an ORDERS05 inbound idoc.
I tried adding a new segment E1EDP01 to the existing idoc in the user exit EXIT_SAPLVEDA_011 assuming that the VA01 posting program would accept the new line item but that approach is not working.
Looking at various posts in the forum, I gather that the best way is to use the function 'BAPI_SALESORDER_CHANGE'. Can anyone please let me know how exactly a new item can be inserted using this function module?
Any help would be appreciated.
ThanksHi Sneha,
Please use the FM 'BAPI_SALESORDER_CHANGE' to add a new line item as under:
CALL 'BAPI_SALESORDER_CHANGE'
EXPORTING
salesdocument = "Pass the Sales order no here"
order_header_inx = "Pass the value of update flag as I as u need to "
"insert a new line item"
TABLES
return = "Will contain the error/success messages"
"after the processing"
ORDER_ITEM_IN = "Here pass the item info tht needs to be added"
Also do a Commit Work after this FM call to reflect the changes in database.
Regards,
Chetan.
PS: Reward points if this is helpful.
Message was edited by:
Chetan H. Dubey -
Is it possible to embed fiori launch pad into portal?
Hi guys,
I'm not familiar with fiori launch pad, how does it work.
But I need a quick feasibility check: is fiori launch pad some kind of an application url?
Can I embed it into somewhere in my company portal?
Regards,
Aaron.Hi Aaron,
Please take a look SAP Enterprise Portal 7.4 SP7 – SAP Fiori Launchpad on the SAP Portal and more....
Regards, Masa
SAP Customer Experience Group - CEG -
HI all,
How to determine or identify the data source required or which fulfils the User requirement.?
Say User from finance wants a Profit center wise report.
and also he wants to see controlling area,costcenter,payment key ,posting methd.....etc.
If we see in R/3 finance data sources,there are 2,3 data sources in which we can find all the above fields?
But how to check or identify the precise datasource which can be taken into BW for report generation?
Is there any standard particular way to identify a datasource which fulfils our requirement?
ThxHi,
If you look at any implementation there is phase for requirement gathering and solution designing ( Business Blue print). The ideal way is get the report requirement from users then look at the ECC data source from functional area perspective. If there is no business user available or not able get the requirements then look for CRP ( Conference room piloting where you activate the complete reporting senarios with sample data and then take the standard delivered reports to business user for feasibility check).
Take a example you mentioning your user interested in profit center report so best way is look at all transactional data sources providing under enterprise profit center. SAP always deliver two types of transactional data sources one for header level/Macro and another for line item level/ detail level. Seat with user and do the feasibility check using RSA2 transaction on ECC side. If you check the profit center reports in finance is wrong. Hence always suggests to seat with business user and SAP functional consultant during requirement gathering and solution workshop. I have seen many failure cases due to this in my last 10 yrs career.
Another way is check all the reports and info providers in help.sap.com>;BI content and do the feasibility check with user requirement before actual BI connect installation. I personally advice don't install the unnecessary objects from meta data repository. Always advisable have the requirement gathering and feasibility/gap analysis study first before moving into actual developments.
I suggest, SAP comes with rich data sources, use the SAP delivered data sources with field enhancements at maximum as per user requirements on top of it. Advisable don't go for entirely generic data source route if possible.
Rgs,
Ambuj Kathuria -
Hi
I am new to the logistics module and have just started learning the PM and CS modules. I was just trying to figure out a query raied by one of the clients regarding a report which will generate the "cost per mile".
Actually the client wants to calculate the cost incurred on the fuel used to run their vehicles. These are fueled from a particular fueling station and the client wants to do a feasibility check on the cost incurred on running the vehicles.
Kindly help me with this. The client is actually looking for a standard SAP report for cost per mile.
ThanksHello,
Also refer this [ THREAD|Re: error in Fleet management customising] and [link|Error when recording measurements in IFCU]
Regards
Nav
Edited by: Desire_Naveen on Nov 4, 2009 12:35 PM -
How do I add a guest user and set it up so that the guest user can use X and all that.
Also, when I start arch it goes directly to console. I like this as opposed to a log in manager. With the help of my fellow archers I added arguments to the xinitrc so that typing "xinit xfce" executes xfce4-session, "xinit X" starts an xterm, etc. etc. Upon starting up I get the login: prompt. Is there any way that I can make it say "type xinit xfce to use the gui, password for guest is blah". Just a small disclaimer to help people who have no idea how to use Linux but want to use my printer.
I've added a guest user before but I could never get the guest user to be able to use X or anything. Any help would be appreciated.
P.S. The guest user is only there because I have the only printer in the house and I don't want to give out my password. Adding a guest user would allow people to print when I'm away.absolutezero1287 wrote:The guest user is only there because I have the only printer in the house and I don't want to give out my password. Adding a guest user would allow people to print when I'm away.
Are all the computerse in the house on the same network? Would setting up your machine to allow other machines to use the printer over the network solve your problem? The latter solution seems much better from many angles, though I don't know what other constraints you're working with. If it does turn out to be feasible, check out samba (assuming the other machines are Windows) or cups. -
Issues with XFA to HTML5 Convertion in Livecycle ES4
We are working on the feasibility check for rendering the dynamic XFA form within our application to enable end user to fill-in and save the form. We used LiveCycle Designer ES4 for designing the forms. Everything works fine with the PC but when tried to load in iPad the form didn’t load at all.
We tried LiveCycle ES4 to convert the file to HTML5 to render in iPad. But it doesn’t look neat as PDF. Listed below the issues we are facing.
1. Data binding not working for few columns though it works perfectly in PDF version
2. Tables are not aligned properly based on the number of rows, the following table/controls getting overlapped on the table.
3. Submit button takes the page to WebAPI (used for Saving the entered form) url instead of saving the content. When invoked from the PDF it saves properly.
Please provide any standards/guidelines for designing the document which will be converted to HTML5 correctly.
Also, we would like to know the pricing of LiveCycle ES4 and is there any lightweight mode available which just does the XFA to HTML5 conversion. The LifeCycle ES4 comes with distributable license?
Regards, JawaharLiveCycle is divided into separate products such as LiveCycle Forms, LiveCycle Output, LiveCycle Rights Management and many more. You may choose the suitable forum from the product list here: Adobe LiveCycle
Good luck! -
Issues with XFA to HTML5 Convertion in Livecycle server
We are working on the feasibility check for rendering the dynamic XFA form within our application to enable end user to fill-in and save the form. We used LiveCycle Designer ES4 for designing the forms. Everything works fine with the PC but when tried to load in iPad the form didn’t load at all.
We tried LiveCycle server to convert the file to HTML5 to render in iPad. But it doesn’t look neat as PDF. Listed below the issues we are facing.
1. Data binding not working for few columns though it works perfectly in PDF version
2. Tables are not aligned properly based on the number of rows, the following table/controls getting overlapped on the table.
3. Submit button takes the page to WebAPI (used for Saving the entered form) url instead of saving the content. When invoked from the PDF it saves properly.
Please provide any standard/guidelines for designing the document which will be converted to HTML5 correctly.
Also, we would like to know the pricing of LiveCycle server and is there any lightweight server mode available which just does the XFA to HTML5 conversion. The LifeCycle server comes with distributable license?
Regards, JawaharLiveCycle is divided into separate products such as LiveCycle Forms, LiveCycle Output, LiveCycle Rights Management and many more. You may choose the suitable forum from the product list here: Adobe LiveCycle
Good luck! -
Replacement of MIRO Invoicing Party (RBKP-LIFNR) with PO Invoicing Party
Hi,
As per one of our business requirement, we want to replace MIRO Invoicing Party (RBKP-LIFNR) with PO Invoicing Party (EKKO-LFRKE) for correct tax calculation during MIRO.
For that we tried to apply BAdis suggested as per SAP Note 1156325 - BAdIs in the Logistics Invoice Verification environment and others. But these BAdis are not enough useful to resolve above problem.
Pls suggest another BAdi / exit for above problem, which can replace MIRO Invoicing Party (RBKP-LIFNR) during MIRO .
Thanks & Regards,
Taral PatelHi,
Thanks for your reply.
below is our business scenario :
"PO is created on branch vendor (with a HO vendor mentioned in master).
While doing MIRO, the system automatically replaces the branch vendor with the Head
office vendor (as mentioned in master). The region taken for tax purpose is the region of the
HO vendor.
for above problem, I have been suggested Note 1156325 from the forum, but none of the BAdi seems feasible (checked with our SAP ABAP Consultant) for this requirement to replace MIRO Invoicing Party (RBKP-LIFNR) with PO Invoicing Party (EKKO-LFRKE).
It would be great help if u can suggest ny BAdi / exit for this requirement.
Thanks & Regards,
Taral Patel -
City code creation in Production
Hi,
One of the requirement from our Sales and Distribution is to make the City code creation as master data in production.
During the feasibility checks I found that it is now being done through view V_T005G and then following the TMS (D to P).
Before I try to customize this, is there a standard tcode/way to maintain the city code creation directly in Production?
How it is being done in other cases?
What is recommended and what will be the impact if we make it as master data?
Thanks in advance, have a good day.
Regards,
Nick LoyNo it is not possible to key in directly in production. As and when you create a new City Code, a transport request would be generated which would then be moved to QA and PRD. Still if you want desperately this data to be maintained without any transport request, then create a zee table and validate this field CITYC value with 4 numeric length. As and when users create data here, in the background, system should update the standard table T005G. But there is a risk involved in giving authorization to create without any transport request.
G. Lakshmipathi -
As-is analysis and Gap Idenificattion
Can anyone please define the terms "As-is analysis" and "Gap identification" in the initial stage of a project? I need to know what they mean and what they consist of.
ThanksHi Gurbinder,
In the As-is analysis you will have to understand the existing business process from user community/conducting workshops and from there you will identify the gaps for the "to be process" to be designed/developed/implemented.
In a BW implementation, after you understand the requirements from As-is analysis, you will have to do a feasibility check by looking at the relevant business content to identify the gaps for possible enhancements/custom developments in the information supply chain (datasources/transfer rules/infosources/update rules/data targets/query components etc.,) for the "to be process" to be implemented.
Hope it clarifies,
Sree -
We've purchase a small BIA (4 blades?), and I am requested to put together a project plan for getting it up and running. Most of the information I can find on the web say it is a plug and play device that can be up and running before dinner (OK, maybe not quite that easy). I know there is much more to it than that, and was wondering if people who have been through it before can give me some tips or pointers as to how long things will take, and what to look out for.
Specifically, I'm wondering how much work does it take from the various teams (Server, Basis, BW), and how long I should expect.
Thanks
MichaelMost of the implementation process will be done by the hardware partner. It is however up to you, the customer, to decide which cubes will be put in the system. Please remember that queries which go against providers such as DSO's or spend much time in OLAP will not be aided by BIA.
Given this I would imagine your business can decide which reports are most critical and need to perform the quickest, so you can work from a top-down approach. For instance, in many cases I've noticed that the cubes behind a CFO's sales dashboard are always indexed
Also if your interested, SAP support actually has a set services to safeguard against any unforseen problems. Contact your CEM (I think they may have a new name now?) and ask about BIA Technicial Feasibility Check. It general it incorporates things such as sizing, query usability and config check.
Edited by: Mike Bestvina on Mar 12, 2008 12:13 PM -
Functional specfication with regard to FICO.
hi,
let me know,
what is functional specfication with regard to FICO.
what is the procedure involved in raising a functional specfication.
which phase in the project we raise the functional specfication.
Regards
Soumyawhat is functional specfication with regard to FICO. : FS is mainly issued by a functional consultant to ABAPer for any customised development(process) or report.
what is the procedure involved in raising a functional specfication.: Normally for the business team a BR(business requirement document is raised) based on feasibility check solution engagement team will raise a CR(change request),so with ref.to CR , related functional consultant will prepare the FS.
FS is outline of the process or the data flow right from selection parameters to the output of the development or report.
which phase in the project we raise the functional specfication.:
For any customisation involved i.e., at the time of final preperation.FS is in short related with ABAP/BI developments or report.
or after Go live also in between they might get specific requirements which might not covered earlier or introduced any new process or derivation of any reports which are not their in the SAP standard IMG activities or reports.
Hope this is clear. -
PAR done but shows PAR Error on planahead 14.7
hi,
am getting PAR error while in log it shows PAR done!!!
this happens only when i change the reset pin of my design from V5 to any other pin.
my design consists of microblaze also.
Thanksfollowing is the logi file
*** Running ngdbuild
with args -intstyle ise -p xc6slx45fgg484-2 -dd _ngo -uc "top_module.ucf" -bm "top_module.bmm" "top_module.edf"
Command Line:
D:\InstalledSW\Xilinx147\14.7\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
-intstyle ise -p xc6slx45fgg484-2 -dd _ngo -uc top_module.ucf -bm top_module.bmm
top_module.edf
Executing edif2ngd -quiet "top_module.edf" "_ngo\top_module.ngo"
Release 14.7 - edif2ngd P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Reading NGO file
"D:/BEL_DRC/BEL_DRC/mohammad_ADC_july24/spartan6_adc2.runs/impl_1/_ngo/top_modul
e.ngo" ...
Gathering constraint information from source properties...
Done.
Annotating constraints to design from ucf file "top_module.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
Done...
Processing BMM file "top_module.bmm" ...
Checking expanded design ...
WARNING:NgdBuild:443 - SFF primitive
'test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Perform
ance.Decode_I/Using_FPGA.Gen_Bits[27].MEM_EX_Result_Inst' has unconnected
output pin
Partition Implementation Status
No Partitions were found in this design.
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 1
Writing NGD file "top_module.ngd" ...
Total REAL time to NGDBUILD completion: 37 sec
Total CPU time to NGDBUILD completion: 9 sec
Writing NGDBUILD log file "top_module.bld"...
NGDBUILD done.
*** Running map
with args -intstyle pa -w "top_module.ngd"
Using target part "6slx45fgg484-2".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 17 secs
Total CPU time at the beginning of Placer: 16 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:1f7146f2) REAL time: 19 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:1f7146f2) REAL time: 19 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:c84c17d2) REAL time: 19 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:fb9deab) REAL time: 38 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:fb9deab) REAL time: 38 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:fb9deab) REAL time: 38 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:fb9deab) REAL time: 39 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:fb9deab) REAL time: 39 secs
Phase 9.8 Global Placement
Phase 9.8 Global Placement (Checksum:fe784d) REAL time: 53 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:fe784d) REAL time: 53 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:bc17e6b8) REAL time: 1 mins 3 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:bc17e6b8) REAL time: 1 mins 4 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:ee3892b6) REAL time: 1 mins 4 secs
Total REAL time to Placer completion: 1 mins 13 secs
Total CPU time to Placer completion: 1 mins 9 secs
Running post-placement packing...
Writing output files...
Design Summary:
Number of errors: 0
Number of warnings: 19
Slice Logic Utilization:
Number of Slice Registers: 2,768 out of 54,576 5%
Number used as Flip Flops: 2,761
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 7
Number of Slice LUTs: 2,495 out of 27,288 9%
Number used as logic: 2,244 out of 27,288 8%
Number using O6 output only: 1,810
Number using O5 output only: 48
Number using O5 and O6: 386
Number used as ROM: 0
Number used as Memory: 157 out of 6,408 2%
Number used as Dual Port RAM: 64
Number using O6 output only: 0
Number using O5 output only: 0
Number using O5 and O6: 64
Number used as Single Port RAM: 0
Number used as Shift Register: 93
Number using O6 output only: 26
Number using O5 output only: 1
Number using O5 and O6: 66
Number used exclusively as route-thrus: 94
Number with same-slice register load: 90
Number with same-slice carry load: 4
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,309 out of 6,822 19%
Number of MUXCYs used: 228 out of 13,644 1%
Number of LUT Flip Flop pairs used: 3,563
Number with an unused Flip Flop: 1,031 out of 3,563 28%
Number with an unused LUT: 1,068 out of 3,563 29%
Number of fully used LUT-FF pairs: 1,464 out of 3,563 41%
Number of unique control sets: 256
Number of slice register sites lost
to control set restrictions: 1,096 out of 54,576 2%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 4 out of 316 1%
Number of LOCed IOBs: 4 out of 4 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 32 out of 116 27%
Number of RAMB8BWERs: 8 out of 232 3%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 14 out of 16 87%
Number used as BUFGs: 14
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 5 out of 8 62%
Number used as DCMs: 5
Number used as DCM_CLKGENs: 0
Number of ILOGIC2/ISERDES2s: 0 out of 376 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
Number of OLOGIC2/OSERDES2s: 0 out of 376 0%
Number of BSCANs: 1 out of 4 25%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 3 out of 58 5%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 4 25%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.63
Peak Memory Usage: 536 MB
Total REAL time to MAP completion: 1 mins 18 secs
Total CPU time to MAP completion: 1 mins 14 secs
Mapping completed.
See MAP report file "top_module.mrp" for details.
*** Running par
with args -intstyle pa "top_module.ncd" -w "top_module_routed.ncd"
Constraints file: top_module.pcf.
Loading device for application Rf_Device from file '6slx45.nph' in environment
D:\InstalledSW\Xilinx147\14.7\ISE_DS\ISE\.
"top_module" is an NCD, version 3.2, device xc6slx45, package fgg484, speed -2
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version: "PRODUCTION 1.23 2013-10-13".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 2,768 out of 54,576 5%
Number used as Flip Flops: 2,761
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 7
Number of Slice LUTs: 2,495 out of 27,288 9%
Number used as logic: 2,244 out of 27,288 8%
Number using O6 output only: 1,810
Number using O5 output only: 48
Number using O5 and O6: 386
Number used as ROM: 0
Number used as Memory: 157 out of 6,408 2%
Number used as Dual Port RAM: 64
Number using O6 output only: 0
Number using O5 output only: 0
Number using O5 and O6: 64
Number used as Single Port RAM: 0
Number used as Shift Register: 93
Number using O6 output only: 26
Number using O5 output only: 1
Number using O5 and O6: 66
Number used exclusively as route-thrus: 94
Number with same-slice register load: 90
Number with same-slice carry load: 4
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,309 out of 6,822 19%
Number of MUXCYs used: 228 out of 13,644 1%
Number of LUT Flip Flop pairs used: 3,563
Number with an unused Flip Flop: 1,031 out of 3,563 28%
Number with an unused LUT: 1,068 out of 3,563 29%
Number of fully used LUT-FF pairs: 1,464 out of 3,563 41%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 4 out of 316 1%
Number of LOCed IOBs: 4 out of 4 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 32 out of 116 27%
Number of RAMB8BWERs: 8 out of 232 3%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 14 out of 16 87%
Number used as BUFGs: 14
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 5 out of 8 62%
Number used as DCMs: 5
Number used as DCM_CLKGENs: 0
Number of ILOGIC2/ISERDES2s: 0 out of 376 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
Number of OLOGIC2/OSERDES2s: 0 out of 376 0%
Number of BSCANs: 1 out of 4 25%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 3 out of 58 5%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 4 25%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Overall effort level (-ol): Standard
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 8 secs
Finished initial Timing Analysis. REAL time: 8 secs
WARNING:Par:288 - The signal test_module_inst/mb_inst/dlmb_LMB_ABus[31] has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[12].ra
m32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[9].ram
32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[13].ra
m32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[7].ram
32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[4].ram
32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal test_module_inst/mb_inst/dlmb_LMB_ABus[30] has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[11].ra
m32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[8].ram
32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[6].ram
32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[5].ram
32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[1].ram
32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[0].ram
32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[14].ra
m32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[10].ra
m32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[15].ra
m32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[2].ram
32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[3].ram
32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
Starting Router
Phase 1 : 20567 unrouted; REAL time: 9 secs
Phase 2 : 15210 unrouted; REAL time: 13 secs
WARNING:Route:436 - The router has detected an unroutable situation for one or more connections. The router will finish the rest of the
design and leave them as unrouted. The cause of this behavior is either an issue with the placement or unroutable placement constraints.
To allow you to use FPGA editor to isolate the problems, the following is a list of (up to 10) such unroutable connections:
Unroutable signal: clk_adc_sig pin: test_module_inst/adc_wrapper_inst/clk_wizard_gen[0].clk_wizard_inst/dcm_sp_inst/CLKIN
Unroutable signal: clk_adc_sig pin: test_module_inst/adc_wrapper_inst/clk_wizard_gen[2].clk_wizard_inst/dcm_sp_inst/CLKIN
Unroutable signal: clk_adc_sig pin: test_module_inst/adc_wrapper_inst/clk_wizard_gen[3].clk_wizard_inst/dcm_sp_inst/CLKIN
Phase 3 : 5729 unrouted; REAL time: 33 secs
Phase 4 : 5729 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 35 secs
Updating file: top_module_routed.ncd with current fully routed design.
Phase 5 : 3 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 49 secs
Phase 6 : 3 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 49 secs
Phase 7 : 3 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 49 secs
Phase 8 : 3 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 49 secs
Phase 9 : 3 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 49 secs
Phase 10 : 3 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 50 secs
Total REAL time to Router completion: 50 secs
Total CPU time to Router completion: 50 secs
Partition Implementation Status
No Partitions were found in this design.
Generating "PAR" statistics.
Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/mb_ | | | | | |
| inst/clk_50_0000MHz | BUFGMUX_X2Y10| No | 960 | 0.064 | 1.774 |
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/adc | | | | | |
|_wrapper_inst/clk180 | | | | | |
| _sig[0] | BUFGMUX_X2Y9| No | 28 | 0.057 | 1.766 |
+---------------------+--------------+------+------+------------+-------------+
| clk_rd_sig | BUFGMUX_X2Y4| No | 104 | 0.052 | 1.770 |
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/adc | | | | | |
|_wrapper_inst/clk180 | | | | | |
| _sig[1] | BUFGMUX_X2Y11| No | 28 | 0.028 | 1.743 |
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/adc | | | | | |
|_wrapper_inst/clk180 | | | | | |
| _sig[2] | BUFGMUX_X2Y1| No | 27 | 0.031 | 1.771 |
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/adc | | | | | |
|_wrapper_inst/clk180 | | | | | |
| _sig[3] | BUFGMUX_X3Y8| No | 27 | 0.028 | 1.739 |
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/mb_ | | | | | |
|inst/microblaze_0_md | | | | | |
| m_bus_Dbg_Clk | BUFGMUX_X3Y13| No | 61 | 0.055 | 1.767 |
+---------------------+--------------+------+------+------------+-------------+
| clk_counter_sig | BUFGMUX_X2Y2| No | 2 | 0.002 | 1.738 |
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/adc | | | | | |
|_wrapper_inst/clkout | | | | | |
| _wiz_sig[1] | BUFGMUX_X3Y5| No | 2 | 0.000 | 1.770 |
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/adc | | | | | |
|_wrapper_inst/clkout | | | | | |
| _wiz_sig[0] | BUFGMUX_X3Y15| No | 7 | 0.045 | 1.767 |
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/adc | | | | | |
|_wrapper_inst/clkout | | | | | |
| _wiz_sig[3] | BUFGMUX_X3Y16| No | 2 | 0.000 | 1.722 |
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/adc | | | | | |
|_wrapper_inst/clkout | | | | | |
| _wiz_sig[2] | BUFGMUX_X2Y12| No | 2 | 0.000 | 1.766 |
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/adc | | | | | |
|_wrapper_inst/clk270 | | | | | |
| _sig[0] | BUFGMUX_X3Y14| No | 4 | 0.022 | 1.765 |
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/mb_ | | | | | |
|inst/microblaze_0_md | | | | | |
| m_bus_Dbg_Update | Local| | 20 | 4.177 | 6.233 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Number of Timing Constraints that were not applied: 1
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
TS_test_module_inst_mb_inst_clock_generat | SETUP | 7.791ns| 12.209ns| 0| 0
or_0_clock_generator_0_SIG_PLL0_CLKOUT0 | HOLD | 0.240ns| | 0| 0
= PERIOD TIMEGRP "test_mod | | | | |
ule_inst_mb_inst_clock_generator_0_clock_ | | | | |
generator_0_SIG_PLL0_CLKOUT0" TS_ | | | | |
sys_clk_pin HIGH 50% | | | | |
TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | MINLOWPULSE | 15.000ns| 5.000ns| 0| 0
pin" 50 MHz HIGH 50% | | | | |
Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_sys_clk_pin
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_sys_clk_pin | 20.000ns| 5.000ns| 12.209ns| 0| 0| 0| 358509|
| TS_test_module_inst_mb_inst_cl| 20.000ns| 12.209ns| N/A| 0| 0| 358509| 0|
| ock_generator_0_clock_generato| | | | | | | |
| r_0_SIG_PLL0_CLKOUT0 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
All constraints were met.
Generating Pad Report.
1 signals are not completely routed. See the top_module_routed.unroutes file for a list of all unrouted signals.
WARNING:Par:100 - Design is not completely routed. There are 1 signals that are not
completely routed in this design. See the "top_module_routed.unroutes" file for a list of
all unrouted signals. Check for other warnings in your PAR report that might
indicate why these nets are unroutable. These nets can also be evaluated
in FPGA Editor by selecting "Unrouted Nets" in the List Window.
WARNING:Par:283 - There are 18 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 53 secs
Total CPU time to PAR completion: 52 secs
Peak Memory Usage: 515 MB
Placer: Placement generated during map.
Routing: Completed - errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 23
Number of info messages: 0
Writing design to file top_module_routed.ncd
PAR done! -
Check the feasibility of dataflow
Hi,
I am under the process of performance optimization of BI system, in this process I will also change the dataflow from 3.x to 7.0.
Now, I have to check the feasibility, whether flow can be upgraded for given specific target.
So, is there any method or process through which I can check the feasibility?
any other suggestion will also be deeply appreciated.
Also, to be more specific I am mainly concerned with FI data.
Thanks,
Saurabh.Hi,
One Quick Suggestion for you.
First, Migrate the transfer rules into transformations before Datasource migration. Otherwise DS migration/activation will become difficult.
Regards,
Suman
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