External clock for PXI-6143

Hi,
I am trying to configure PXI-6143 to use an external clock exported from an arbitrary waveform generator (PXI-5412). I followed the example code (Fgen DAQmx Synchronization.vi) and use one of the RTSI trigger line for exporting the clock, but couldn't get it to work. When I run the attached code, it returned an error saying not enough samples were collected by the AI task, but the samples are returned correctly if I just let PXI-6143 use its internal clock. Could someone point out what goes wrong in this code, please?
Thanks!!
Solved!
Go to Solution.
Attachments:
sync_fgen_ai.vi ‏51 KB

Sorry, just realized that I posted the wrong code.
Attached is the correct version with the clock source configured to one of the RTSI lines.
Thanks!
Attachments:
sync_fgen_ai_working_with_internal_clk.vi ‏53 KB

Similar Messages

Want to use external clock for SCTL on myRIO

Hi people,
I'm trying to find a way to get a 2.5 MSPS 16-bit ADC, TI ADS1602, to send data to the myRIO device. Ideally, I want to record bits at 40 MHz in order to get the benefit of the full 2.5 MSPS. I know that I can create an 80 MHz SCTL on the FPGA to create a 40 MHz clock, but when I checked this clock signal on an oscilloscope it was obviously significantly degraded by slew rate limitations, so it looked more like a sine wave than a square wave. I doubt that it would work to use this signal as a clock to drive the ADC, since the ADC's specifications say the allowable jitter is around 100ps.
I can use an external oscillator to drive the ADC, but then I have to find a way to sync that clock with the 40MHz FPGA clock. Is there any kind of PLL structure that would allow me to sync the myRIO FPGA clock to an external clock? Is there a way to make a single cycle timed loop be driven by an external clock? Or if I was able to customize the FPGA personality to accept an SPI signal of up to 40 MHz (ten times the officially supported limit...), would it be ok to use an FPGA loop running at ~160 MHz and tell it to sample the SPI line each loop and proceed from there?
Thanks!
Solved!
Go to Solution.

Hi 3.14159... ,
The myRIO does not have the ability to import a clock to use on the FPGA Block Diagram to clock single-cycle timed loops (SCTLs). The new sbRIO-9651 that just released at NI Week (not shipping yet) is the only sbRIO that has the ability to import an external clock into LabVIEW. Several of our FlexRIO products also have this ability.
As you alluded to, you can sample the signal at twice the frequency (or possibly more) to and wait until an edge trigger to execute a certain piece of logic. If you open the Example Finder and navigate to Hardware Input and Output » R Series » FPGA Fundamentals » Triggers and Watchdog » Trigger Detection this gives a simple example of doing that. Again, since you are wanting to sample at 10x the supported frequency, all bets are off but it may be worth a try.
Tannerite
National Instruments

Configure digital filter for external clock

I am trying to use a digital filter on my PXI-6602 card and I can't get it to configure for an external clock. It keeps telling me the numbers don't match up but I don't see the logic to the numbers it supports. Here is the error I got for a time base of 100 Hz and a min pulse width of 1/(100 / 2) based on the period of 2 clock cycles.
Desired Minimum Pulse Width could not be produced.
Minimum Pulse Width is affected by the Digital Filter Timebase Source and the Digital Filter Timebase Rate. To see how these two property settings can affect the Minimum Pulse Width, refer to product documentation for more details.
Property: CI.CountEdges.DigFltr.TimebaseSrc
Requested Value: /PXI1Slot2/PFI36
Property: CI.CountEdges.DigFltr.TimebaseRate
Requested Value: 100.000000
Property: CI.CountEdges.DigFltr.MinPulseWidth
Requested Value: 20.0e-3
Supported Values: 80.0e-3 to 171.798692e6
Task Name: _unnamedTask<49>
I know my math is off since the filter uses the leading edge of the pulse but 0.08 seconds is 12.5 Hz and I don't get it. Other frequencies produce different but also odd (to me) numbers.
Attached is a copy of my VI
Attachments:
External Clock for Filter.jpg ‏131 KB

Digital filtering ensures that a high pulse is high for at least a certain time (minimum pulse width) in microseconds. This is to ensure that a fluke noise signal does not count as a high pulse. It also ensures that a voltage overshoot to the high value does not register more than one high pulse as it settles in to the value.
The specifications of the digital filtering is outline on page 3-1 to 3-3 of the 660x User Manual, found here. It specifies on page 3-3 that there are five different settings for the digital filter minimum pulse width:
5 µs
1 µs
500 ns
100 ns
Or, programmable with a custom tfltrclk (period in seconds of Filter Clock). However, when using tfltrclk, minimum pulse width needs to equal to 2*tfltrclk. Your current setup has the minimum pulse width set up for minimum pulse width = 1/(tfltrclck/2) = 2/tfltrclck rather that 2*tflrclk.
I think you already knew all of this. However, the Filter Clock does not equal the Filter Clock Timebase.
If we look on page 3-3 in the manual we seed that Filter clock is actually 1/4th the speed of the Filter Clock Timebase.
Therefore, in your setup:
Filter Timebase Rate = 100Hz
Filter Clock Rate= 1/4th *100 Hz = 25Hz
Filter Clock Period = 1/25Hz = 0.04 seconds
2*Filter Clock Period = Minimum Pulse Width = 2*0.04=0.08 seconds.
Which is the minimum value it was suggesting. This will always be four times as large as what you were guessing before.
Eric S.
AE Specialist | Global Support
National Instruments

5122 External Clock Questions

I am working on a project that requires the ext. clock (100Ms/s on a
5122) and a signal hand-off. Signal 1 is 32MHz, and Signal 2 is
32MHz +- 100,000Hz. If I am feeding in Signal 1, what is the
minimum and maximum times I have to kill signal 1 and input Signal 2 so
that the card doesn't crash. In other words, the jitter
parameters on the PXI 5122 clock. I cannot find this information
anywhere. If I had to guess, the minimum time would be 1/105MHz =
9.5ns and the max would be 1/30MHz = 33.3ns. The 30MHz and 105MHz
comes from the PXI 5122 data sheet.
Also, if the hand-off were made smoothly withing the jitter
specification times, would the clock crash due to the change in
frequency between the 2 signals?
Thank you for your time,
Austin McElroy

*I have posted the answer on all 3 of the forums that you queried, but please continue the thread here, in the appropriate section:*
Good morning Austin,
Thanks for contacting National Instruments with your issue, we'll try our best to solve it for you as quickly and efficiently as possible.
I'm going to have to contact R&D about this specification. There are some that might get us close, such as the fact that the PLL Reference Frequency has to be accurate to +/-50 ppm (page 14 of (http://digital.ni.com/manuals.nsf/websearch/5D8BAB258130779686256FA800691AAA)) and that the sample clock delay range is 1 sample clock period (Page 13), that I could postulate on, but I'd rather get the definitive answer.
One point of helpful clarification would be whether you're using the external clock for the reference clock or sample-clock timebase.
I will let you know as soon as I hear anything from R&D.
Sincerely,
Minh Tran
Applications Engineering
National Instruments

External clocking on 6711 card

Hi all,
I just read the manual of the card PCI6711, it supports the external clock. So does it mean we can change the update rate by using different external clock rate?

chris88 wrote:
HI dragondriver
They are both correct, the PCI 6711 supports external clocking for the analog output tasks, but for Digital I/O tasks the timing can only be set to software timed, meaning that you cannot use external clock for digital tasks.
The main difference between RTSI and PFI is the physical connection, PFI lines conects through the connector block you are using and the RTSI is connected through a RTSI bus cable used to synchronize several DAQ cards.
You can choose any PFI <0 to 9> and this article show how to select which PFI line is the source of sampling.
Regards
Thanks for the clarification . I only one doubt. Someone told me that 6711 only supports software-based digital pulse input/output but it supports external-clock-driving counter output. So when you said softwarebased digital I/O task, do you mean all digitals output including counter output? Thanks.

Setup external clock

I just bought a GENx192 by lucid. I was having problems with the projectmix and my audio. So I went and picked up a better clock. But now Im wondering how to hook it all up. I have it hooked up I think. But do I have to set the sample rate on both the GENx and in logic or if I have it sync right should I be able to just set the GENx and Logic should change also. Thanks.
I cant remember the name of the cable that I use but its a monster cable and it is the right one thats for sure.

I have an iMac (Intel) running Tiger 10.4.11 and when I have a digital input to this Mac I can see the signal is going in on the input meter in the iMac. But the clock source "default" is greyed out. But it must be clocking to this audiio... I figure... otherwise it would not sync to it. When I remove this input I cannot select external/digital clocking. When I connect a firewire digital audio interface and select properties for it I can select clocking for it either internal or digital.
But my real problem is on a Mac Pro running Leopard 10.5.3. On this Mac it seems to me that I cannot select external or digital clocking under any conditions.
And I am wondering if a change has been from Tiger to Leopard such that there is no option to select digital/external clocking for audio. That is the crux of my question?

Is the PXIe-PCIe8361 adequate for this system? And external clock questions...

Hi all,
I have spent some time piecing together a system and I'd like a sanity check before pulling the trigger on this purchase. The system will contain the following hardware:
1. Chassis: PXIe-1078
2. Controller: PXIe-PCIe8361
3. 3 x PXIe-6363 (16 analog inputs each card, 32 digital inputs each card, all internally clocked @ 10kHz)
4. 2 x PXI-6224 (32 digital inputs on one, 8 digital inputs on the other, externally clocked in "bursts" of 62.5khz)
5. Labview software
The three PXI-6363 cards will be responsible for a mix of analog and digital measurements made @ 10 kHz, timed continuously by the onboard clock.
One PXI-6224 will be clocked externally @ 62.5 kHz and will be used to collect digital data on a 32-bit port. These clock pulses will not be continuous, but will occur in bursts lasting for 2ms every 20ms.
The other PXI-6224 will be clocked externally @ 62.5kHz as well and will be used to collect digital data on an 8-bit port. These clock pulses will not be continuous, but will occur in bursts lasting for 2 ms at random intervals.
My questions are:
1. Am I planning anything that looks unreasonable for this hardware?
2. Should I expect issues with data transfer rates with the PXIe-PCIe8361? I will be operating well within the advertised 110MB/s throughput of the device. I plan to stream this method... NI Fast TDMS data streaming
3. I have only ever used NI cards for continuous measurements made by an onboard clock. When I set up a task to collect data that is externally-timed, will the DAQ be expecting a "continuous" clock pulse, or will the system wait patiently for clock pulses to arrive at any rate (any rate within the spec of the card, of course)?
Thanks, any input is appreciated.

Hello LucasH0011
1-As long as you put the PXI-6224 and the PXIe-6363 cards in the corresponding slots, meaning the express(PXIe-6363) in the express and the hybrid(PXI-6224) in the hybrid.
2-I think you would not have issues with the transfer rate.
3-Your timing specifications sound reasonable to me, I think you will be fine.
Here is a document that has useful concepts for the use of cards:
http://www.ni.com/white-paper/3615/en/
It is for the M-Series, but the concepts apply to the X-Series as well.
Regards
Ernesto

Using an external reference clock for counter measurements

Hi all,
I have several PXI chassis
configured for testing, each of which uses an NI-DAQ-6221 for
conducting period and frequency measurements among other things.
However each of my setups give me a slightly different reading when conducting identical measurements due to
the tolerance of the DAQ on board reference
clocks.
The chassis' have a 10MHz GPS calibrated reference fed into them via the reference input and this is connected to the backplane. I have tried and failed to try to route and use this as my reference
base for my counter measurements so that each of my cards will give me
the same reading every time. I have tried the routing method using the
DAQ connect terminals vi but could not get this to work. I have looked through the labview examples and cant find anything thta shows me what i need to do to take frequency and period measurments using my external reference as my base clock. There are some examples showing the use of the DAQmx timing vi set to sample clock mode which allows a clock source to be selected. However these examples are only for counting digital events and when i apply the same vi to a frequency or period measurement an error is thrown saying 'invalid timing type for this channel', 'you can select: implicit, on demand'.
I do not
understand the working of the DAQ hardware very well so was hoping
someone could help explain to me how to do this if it is even possible
or give me any guidance as to how else to overcome my problem. Any vis
showing how to use my external 10MHz reference
as the base clock for these kind of measurements would be greatly appreciated.
Regards,
Dan

Hi Dan,
Thanks for the reply. When trying to use the connect terminals i just tried connecting the PXI10 to the onboard clock in the hope that this would configure it to use the PXI10 signal to synchronise the onboard clocks via the PLL. Doing this didn't throw any errors as i recall, it just gave me a reading of infinity as it couldn't measure the signal.
I have actually just managed to successfully do what i wanted thanks to help from Rob at NI tech support UK. There is a DAQmx timing property node which allows you to choose a reference clock source. By using the PXI_Clk10 signal this makes the DAQ synchronise its reference clocks to this signal. I have included an image of the code i used to achieve this to take period measurements.
Here is a very useful link which Rob sent me which may be of help to anyone else with similar problems
http://zone.ni.com/devzone/cda/tut/p/id/3615
Best regards,
Dan.
Attachments:
ExtRef Source Image.jpg ‏105 KB

How to use PXIe 5652 as external clock to the USRP

Hi,everyone,I'm new to PXI and USRP,and there are some problems I want to ask for help.
What I want to do is to synchronize 8 USRPs which are used as receivers. To make sure they have the same crystal oscillator, I want to use the PXIe 5652 as the external clock.However, what confuse me are that PXIe 5652 has 3 connector(RF out, REF in/out, REF out2), and USRP 2920 has REF in and PPS in, how to connect them? Wheather I need to connect the PPS in to achive my aim? And,if it is needed to write some labVIEW programs to make PXIe 5652 as the external clock? that's all,thank you!

Hi,
To provide a external reference frequency signal I think the following method can be used.
Use the niRFSG or niRFSA Export Signal VI to export the "Reference Clock" signal to "RefOut" or other appropriate output terminal.
Use the commit VI to commit these settings to the driver.
For ease you may use one of the existing RFSA or RFSG example VIs and add the export signal and commit VIs.
When the VI which opens a session to the RFSG or RFSA device is run the reference clock signal shall be exported to the configured terminal of the RFSA or RFSG device.
You may then connect this terminal to the Ref In terminal of your USRP device which you would have configured to use a external reference frequency source.
This method works for the VST which I use.
Thanks.

NI 5772, using clk_in as an external clock

Hi.
I'm using NI 5772R with NI PXIe-7966R NI FlexRIO FPGA Module.
I'm trying to sample the signal with external clock (CLK_IN). An example file 'Clock Select (FPGA).vi' is successfully compiled. However when running 'Clock Select (host).vi', the data doesn't seem to be sampled with CLK_IN signal even if I choose the clock source as 'External Clock'. Actually externally clocked data is the same as internally clocked data.
So I wonder if this is because the signal plugged into 'CLK_IN' has wrong range. The frequency range of my CLK_IN signal is 80~160MHz, while the specification of NI5772 says the CLK_IN input range is 400-800MHz. Would it be a problem?
Also, My clock signal is sinusoidal, rather than TTL. Does the CLK_IN need to be TTL?
Thanks for your help.

Yes the output impedance of the amplifer is designed 50 ohms, so that is not an issue ...
We have hooked it up to a function generator, and gotten it to work at 500 MHz even at the lower voltages.
After unplugging the function generator, then plugging in our external clock, it will run, by the signal is corrupted at several points.
The long period duty cycle of the clock is only about 60% (i.e. there is a log period where no clock signal is sent)
I think the issue may also have to do with the clock phase, which is not unform. The NI 5772 uses a Texas Instruments ADC . Reading the manual for tha part, it seems like the clock requirements are pretty tight, as it is expecting a very low jitter clock signal
Another group we work with has a digitizer made by another company that apparently solves this issue by routing the clock though a VCO, which somehow stablizes the clock. However, after some consultation we are not convinced that is the real solution either, because the clock is supposed to be somewhat unstable in the first place, which is the issue we are trying to correct for (we are trying to avoid having to resample the data in software)

Using an external Clock with NI 6585

I have an interface board connected to a TI ADS6444 Evaluation board (QUAD serializer ADC), in turn plugged into my NI 6585/PXI-7954R, see the Project Screen shot. I can acquire data using internal clock but now I want to switch to an external clock. First I want to get the external clock working then do the unserializing. I am quite new to LabVIEW FPGA.
I get a variety of errors such as " The Read method for IO Module\DDCA_Data_Rd_Rise is used in a clock domain that does not support it. The supported clock domain is "IO Module Clock 0". To change the frequency of the supported clock domain, launch the properties dialog for the CLIP item in the LabVIEW project and choose the "Clock Selections" page." I have tried to configure the clock to fixed and variable frequencies, see clock properties screen shot.
Thanks in advance.
LeMur Technology Services, LLC
President
[email protected]
Toll Free: 877-761-2916
Cell: 609-577-2628
Fax: 215-862-9816
Attachments:
Project screen shot.jpg ‏164 KB
clock properties screen shot.jpg ‏77 KB

Update
Opened a service request. for this problem. Talked it over with NI engineer and thought the problem was because I disn't have the latest and greatest software versions e.g. RIO and LabVIEW. Compiled a blank VI using the DDC connector and comilied successfully. No matter what I do if I do a FPGA I/O Node call to DDCA_Data_RD_RISE (or fall) I get the error: "The Read method for IO Module\DDCA_Data_Rd_Fall is used in a clock domain that does not support it. The supported clock domain is "IO Module Clock 0". To change the frequency of the supported clock domain, launch the properties dialog for the CLIP item in the LabVIEW project and choose the "Clock Selections" page."
For grins I wired the FPGA I/O node Expected I/O module ID to the FIFO input and read a number (7488[HEX]).
Begining to suspect the NI 6585 CLIP has a bug?
LeMur Technology Services, LLC
President
[email protected]
Toll Free: 877-761-2916
Cell: 609-577-2628
Fax: 215-862-9816

Quadrature Encoder measurements with PXI-6143 S-Series DAQ

Has anyone used a S-series PXI-6143 DAQ to take encoder position measurements? I believe there are 2 counters available, if you have any examples of how to access and read from these counters it would be greatly appreciated.

Hi Bentup,
Measuring a quadrature encoder on your device is actually going to be a bit different than on an M series device. The STC-2 chip, which is used in the M series, allows for A and B inputs specifically for encoder signals (used in the Angular Encoder task). The original STC-1 chip which is used in E series and most S series boards (including your 6143) does not have these same inputs. Instead, you may must a Count Digital Events task (taking advantage of the up/down line of the counter). The Angular Encoder task is not supported on STC-1 devices.
The article that lab_boy linked earlier actually mentions how to use an encoder with an E series device once you scroll down a bit (here's the link again). This same procedure should apply to your S series--connect the A output of your encoder to the source of the Counter (this is the signal that you are counting). Connect B to the up/down line of the counter (P0.6 and P0.7 for counter 0 and 1 respectively).
The downside with this method is that it is more susceptible to vibrations or noise on the encoder lines. If this is a problem for you, you can look into an external encoder conditioner like the one mentioned in the article. I hope this helps!
Best Regards,
John
John Passiak

How I can measure frequency of TTL signal without external clock?

Hello,
I want to measure frequency of TTL signal using PXI-6254 or PXI-6713, without using external clock.
Frequency will be up to 100kHz. How I can use internal counter of 20MHz or 80MHz?

Hi Yuta K,
You have not stated what software you want to use for this measurement, but in case you're using LabVIEW, please go to the Example Finder (in LabVIEW go to "Help >> Find Examples").
In the Example Finder, you make sure the "Browse" tab is stil selected, and than you go to:
Hardware Input and Output >> DAQmx >> Counter Measurements >> Digital Frequency
Here you will find some good examples of measuring a digital frequency with 1 or 2 onboard counters.
If you need additional information, please let us know!
Best regards,
Peter S

How can I use external clock to implement a delay?

Hi all,
I am testing to use external clock to drive dev/PFI0 (on device 6711) which is used as the clock for the analog ouput. I have thinking two applications by using the external clock but I don't have much idea on the implementation yet.
First of all, I have a sequence of data (array) with each sample being sent at the interval of 1us. I use an external clock (10MHz) driving the PFI0 so it is pretty easy to achieve that goal. I am thinking what happen if I want each sampel being sent at different time. For example, if I have 5 samples, I want the first one sent 1us after the task start and wait 2us to send the 2nd sample, wait 5us to send the 3rd sample and wait 11 us to send the 4th sample, and wait 1us to send the last sample. Is it possible to achieve that based on the external clock?
Second question is about the delay. My code require ciritcal timing and the builtin delay doesn't behave very well because I am running in windows. I can increase the priority of the vi to highest, it helps a bit but still not perfect. I am thinking if it is possible to implement hardward delay based on the external clock. Any idea?

Hello dragondriver,
To answer your first question, yes you could send data in that fashion. You would have to programmatically build a pulse train and use that to trigger the sending of data. The answer to the second question is essentially the same. You should be able to programmatically build a pulse train with a delay and use it as trigger to begin whatever operation you have.
Jonathan L.
Applications Engineer
National Instruments

How to use external timebase for Two Edge Separation measurement with PCIe 6351

Hi
I am working with PCIe 6351 x series DAQ card.
counter measurements.
Here i need to measure the time/no edges between two edges. Falling to Raising of two signals.
I got the measurement with internal time base.
here i need to synchronize the measurements with external clock from the external setup.
so i need to use that external clock,timebase for the counters.
Any solution please..
Regards,
Hari

First, the VI you mention is NOT for STC timer/counters. Therefore, it won't work.
If you want to get the time interval between two edges, you want to use the Functions -> Data Acquisition -> Counter -> Count Events or Time VI. This will do the function you are looking for.
Mark

External clock for PXI-6143

Similar Messages

Maybe you are looking for