Converting async to sync nrz external clock

Hi, I am reading data through a RS-232 to RS-422 using a B&B electroncs converter. However when Iread the data through the VISA it comes in asynchronous, and I need it to be synchronous with NRZ (Non-Return to Zero). I am having trouble figuring out how to make this conversion. If anyone has any experience with this or any idea as to how to make this happen I would appriciate the help.

Hello,
VISA will only read what has been transmitted to and from you COM Port, the mode of transfer, asynchronous or synchronous is not controlled by VISA.
National
Instruments serial hardware is designed to be 100% compatible with the
serial ports that are built-in to your standard PC. These ports use the
8250 UART (Universal Asynchronous Receiver/Transmitter), which is
asynchronous. This could also apply to the hardware you are currently using.
You may want to contact the manufacturers of your device.
Christian A
National Instruments
Applications Engineer

Similar Messages

Ni5640R sync with external clock

Hi,
I have a highly stable 10MHz sine source, and I need to phase-lock NI5640R's internal 200MHz generator to it.
I don't really understand half of the parameters in "Config Timebase". Any advice on how to do this?

As I understand it, in:
CDC Clock Source tab:
* Clock Source = VCXO, since I need not external clock, but internal oscillator locked on external signal
VCXO tab:
* VCXO Control = PLL, since VCXO frequency will be controlled by external clock via PLL
* VCXO Enable = ON, obviously
Reference tab:
* RTSI Ext Ref Enable = OFF
* SMB Ext Ref Enable = ON, since this is the external signal source
* Clk100 Ref Enable = OFF
* RTSI(7) Direction = OFF, don't know what it is, but doesn't seem relevant
PLL tab:
* Ref Delay = 0ps, I only care about phase stability at the moment, so delay is not relevant
* VCXO Delay = 0ps, same here
* Ref Divider = 10, this divides 10MHz external reference to get 1MHz
* VCXO Divider = 200, this divides 200MHz internal generator to get 1MHz, then both 1MHz freq's are synchronized
* CP Current = 2.5mA, but I have no idea what this does
* CP Enable = NO, no idea
* CP Invert = NO, no idea
* PFD Pulse Width = 1500ps, (CDC7005 datasheet states, that PFD pulse is something that improves spurious suppression) I have no idea how wide the PFD pulse should be, I guess it depends on external source quality
* Lock Detect Window = 1.2ns, as I understand it, PLL is considered locked when rising edge of controlled signal of is in this window, so smaller window means less jitter
Routing tab:
* PLL Feedback Channel = Y2, this is by default, I don't know if this should be touched. This is also a bit confusing, since the choice is between [Y0, Y1, Y2, Y3, Y4, Y3, Y3, Y3]. I wonder how these Y3's are different?
* Y0 (ADC0) Division = divide by 2, Y0 Enable = YES, I see no need to modify this
* Y1 (ADC1) Division = divide by 2, Y1 Enable = YES, same here
* Y2 (DAC0) Division = divide by 2, Y2 Enable = YES, same here
* Y3 (DAC1) Division = divide by 2, Y3 Enable = YES, same here
* Y4 (RTSI Ref) Division = divide by 2, Y4 Enable = YES, same here
Misc tab:
* OPA Enable = FALSE, OPA is a enable/disable control for amplifier. I'm not really sure about what it does and if this is even connected in NI5640R, default is off
* Enable Ext Ref R = FALSE, may be something related to what I need, by default it is off
* Hold = FALSE, as I understand, when this is enabled, PLL tries to maintain lock when missing reference cycle, probably may be used for clock extraction from serial data stream. for this application it's not necessary
* NPD = TRUE, according to CDC7005 datasheet, NPD is asynchronous power down, and should be held high
* NRESET = TRUE, asynchronous reset signal, should be held high
* Bandgap Enable = TRUE, not sure what bandgap is, and I don't think it's relevant
External tab:
* HW NPD = TRUE, should be hardware power down
* HW NRESET = TRUE, hardware reset

Is it possible to read digital data using an external clock (PCI-6259 M)?

I’m using a NI PCI-6259 M Series card and trying to write my program in VC++6.0 using the functions in the DAQmx driver.
Question1: Not all functions listed in the NI-DAQmx C Reference Help seems to be supported by my NI-card, where can I find information about which of the functions that are supported?
Question2: I want to read data from a device that clock out data on the falling edge of a clock signal. The clock signal and the data signal are routed to two DIO terminals on the NI-card. The question is if it is possible to read data using the clock as a sample clock? See two code examples below that doesn’t work. In both cases 10 samples are read at once, even if the external clock is not present.
Example 1
// Create tasks
Status = DAQmxCreateTask("", &m_ReadTrimTask);
// Set up read task
status = DAQmxCreateDIChan(m_ReadTrimTask, "Dev1/port2/line0", "", DAQmx_Val_ChanPerLine);
status = DAQmxCfgChangeDetectionTiming(m_ReadTrimTask,"Dev1/port2/line6","Dev1/port2/line6",DAQmx_Val_FiniteSamps, 10);
// Read data
int32 sampsPerChanRead, numBytesPerSamp;
status = DAQmxReadDigitalLines(m_ReadTrimTask, 10, 10.0, DAQmx_Val_GroupByChannel, result, 10, &sampsPerChanRead, &numBytesPerSamp ,NULL);
Example 2
// Create tasks
Status = DAQmxCreateTask("", &m_ReadTrimTask);
// Set up read task
status = DAQmxCreateDIChan(m_ReadTrimTask, "Dev1/port2/line0", "", DAQmx_Val_ChanPerLine);
status = DAQmxSetSampTimingType(m_ReadTrimTask, DAQmx_Val_SampClk);
status = DAQmxSetSampClkRate(m_ReadTrimTask, 1000.0);
status = DAQmxSetSampClkActiveEdge(m_ReadTrimTask, DAQmx_Val_Falling);
status = DAQmxSetSampClkSrc(m_ReadTrimTask, " Dev1/port2/line6");
// Read data
int32 sampsPerChanRead, numBytesPerSamp;
status = DAQmxReadDigitalLines(m_ReadTrimTask, 10, 10.0, DAQmx_Val_GroupByChannel, result, 10, &sampsPerChanRead, &numBytesPerSamp ,NULL);

Hello Magnus,
Thank you for contacting National Instruments.
"Question1: Not all functions listed in the NI-DAQmx C Reference Help seems to be supported by my NI-card, where can I find information about which of the functions that are supported?"
The best place to look for this information would be the M Series Help Manual. There you can find the features of your PCI-6259 and what operations it supports.
"Question2: I want to read data from a device that clock out data on the falling edge of a clock signal. The clock signal and the data signal are routed to two DIO terminals on the NI-card. The question is if it is possible to read data using the clock as a sample clock? See two code examples below that doesn’t work. In both cases 10 samples are read at once, even if the external clock is not present."
Look at the "ContReadDigChan-ExtClk_Fn.c" example project which ships with the NI-DAQ driver. This is located at: C:\Program Files\National Instruments\NI-DAQ\Examples\DAQmx ANSI C\Digital\Read Values\Cont Read Dig Chan-Ext Clk.
You will have to make some minor modifications to convert this to a finite acquisition, but that is simply a matter of changing the "sampleMode" parameter of the DAQmxCfgSampClkTiming() function. You will also have to route your clock signal to a PFI line and specify which line in your code.
I hope this helps.
Sean C.
Applications Engineering
National Instruments

Async To Sync

Hello,
using jdev 11.1.1.4
i mistakenly created a Asyc BPEL process. process is ready and working
I want to now convert it to sync process, without impacting the functionality. what is the best way to convert async process to sync process ? How do i achieve this single click using Jdev ?
thx

I doubt this is possible using a single click in WSDL. However there is an article explaining this.
http://orasoa.blogspot.com/2007/03/convert-synchronous-proccess-to.html

Domain Controller - Time Syncing with CMOS Clock

Hello!
We have a DC that is syncing time from "local CMOS clock." This DC is a VM (hyper V). Integration services has "time sync" turned off.
I've attempted syncing the DC to an external time source per http://www.thirdtier.net/2011/02/how-to-set-an-ntp-time-server-in-windows-2008-sbs-2008-and-sbs-2011/ and the issue persists.
Also of note - I've attempted syncing the VMHOST to an external source as well, and it is only syncing with CMOS clock
w32tm /config /manualpeerlist:"time.windows.com" /syncfromflags:manual /reliable:yes /update
- results>
I manually restarted Windows Time service, still syncing to CMOS
w32tm /resync /rediscover
- results>
the computer did not resync because no time data was available
w32tm /stripchart /computer:time.windows.com /samples:5 /dataonly
- results>
Tracking time.windows.com [65.55.56.206:123].
Collecting 5 samples.
The current time is 4/14/2014 12:34:41 PM.
12:34:41, -16.0686354s
12:34:43, error: 0x800705B4
12:34:46, -16.0885249s
12:34:48, -16.0981303s
12:34:50, -16.0785199s
w32tm /monitor
- results>
EVEREST.COMPANYNAME.local[192.168.45.34:123]:
ICMP: 0ms delay
NTP: +17.4000482s offset from COMPANYNAME-DC1.COMPANYNAME.local
RefID: 'LOCL' [0x4C434F4C]
Stratum: 1
COMPANYNAME-DC1.COMPANYNAME.local *** PDC ***[192.168.45.31:123]:
ICMP: 0ms delay
NTP: +0.0000000s offset from COMPANYNAME-DC1.COMPANYNAME.local
RefID: 'LOCL' [0x4C434F4C]
Stratum: 1
COMPANYNAME-MGMT.COMPANYNAME.local[192.168.45.33:123]:
ICMP: error IP_REQ_TIMED_OUT - no response in 1000ms
NTP: error ERROR_TIMEOUT - no response from server in 1000ms
COMPANYNAME-DS1.COMPANYNAME.local[192.168.45.32:123]:
ICMP: 0ms delay
NTP: +14.7149589s offset from COMPANYNAME-DC1.COMPANYNAME.local
RefID: 80.84.77.86.rev.sfr.net [86.77.84.80]
Stratum: 2
EVEREST.COMPANYNAME.local = 2k3 box
COMPANYNAME-MGMT.COMPANYNAME.local = old DC improperly removed from domain (aka was just deleted from Hyper V by another technician...)
COMPANYNAME-DC1.COMPANYNAME.local = primary "main" DC, 2k8
COMPANYNAME-DS1.COMPANYNAME.local = backup DC, 2k8
I can provide whatever other info that may prove useful. I've looked @ other posts RE: this issue and feel like I might be missing something obvious, but I am at a loss.
Thank you!

Hi,
Is UDP 123 open on the machine? I suggest you try to disable firewall to see if it works.
More information for you:
Can't get NTP time working on SErver 2008 R2 DC
http://social.technet.microsoft.com/Forums/windowsserver/en-US/e5e26e4f-1988-4ec1-8837-6d1d503130e7/cant-get-ntp-time-working-on-server-2008-r2-dc?forum=windowsserver2008r2general
Configuring the Windows Time Service for Windows Server
http://msmvps.com/blogs/acefekay/archive/2009/09/18/configuring-the-windows-time-service-for-windows-server.aspx
Error message when you run the "w32tm /resync" command to synchronize Windows Server 2003 or Windows SBS to an external time source: "The computer did not resync because no time data
was available"
http://support.microsoft.com/kb/929276
Time synchronization is not performed even though the W32Time service is successfully started in Windows Server 2008 or in Windows Server 2008 R2
http://support.microsoft.com/kb/2493006
Best Regards,
Amy

External Clock PCI-6110

Hello / Bonjour
I am using Labview 6.1 / Window 2000 and a NI PCI-6110 card.
The system that I develop uses an external clock (connected to the PFI7) to sample a signal in channel 0, a trigger connected to TRIG 1 starts an acquisition. The program controlling the DAQ is a modified version of “Acquire N Scans ExtScanClk D-Trig.vi” example, I have removed from this example the two sub-vi “AI Clock Config”. The program uses then the STARTSCAN signal as an external clock.
I have three questions:
1 How do you configure STARTSCAN to either the rising or falling edge polarity as it is stipulated in the pci-6110 user manual?
2 What is the purpose of the two sub-vi “AI Clock Config” in the “Acquire
N Scans ExtScanClk D-Trig.vi” as it seems the PCI-6110 card doesn’t need them to run properly with an external clock?
3 Should I configure the CONVERT* signal if I would like to sample the channel 0 signal immediately when a STARTSCAN pulse appears?
Thank you

Thank you rgharrison for your answer
I tried to make some modifications and tests following your comments.
I have incorporated the �AI Clock Config� in my application (which is now very similar to �Acquire N Scans ExtScanClk D-trig.vi� except that there is only one �AI Clock Config� VI) and I have these questions and comments:
As the PCI-6110 samples each channel simultaneously (and I want to sample only one channel), should I set the channel clock as you mentioned?
Given that my external clock is connected to PFI7 and I have specified �PFI pin, high to low� in �clock source code�, it doesn�t matter for the board if I set any PFI as �clock source string�: my board still find an external clock. But if I leave �clock source string� blank I�ve got
an error. I noticed also that the parameters of the �actual clock rate specification� cluster are still equal to zero. Is it normal or I misunderstand something?
I don�t understand why I should set up the �clock source� as fastest as possible, as I want to use an external clock and sampling my signal one time per external clock period. Also, in the �Acquire N Scans ExtScanClk D-trig.vi� exemple, after set the clock as fast as possible, the following VI �Ai Start� disable the internal clock, so again why set up the clock and disable it just after?
If I set the �clock source� at the maximum rate and if the scan clock (my actual external clock) is slower than the �clock source�, can the board acquire more than one sample by external clock period?
Regards

Want to use external clock for SCTL on myRIO

Hi people,
I'm trying to find a way to get a 2.5 MSPS 16-bit ADC, TI ADS1602, to send data to the myRIO device. Ideally, I want to record bits at 40 MHz in order to get the benefit of the full 2.5 MSPS. I know that I can create an 80 MHz SCTL on the FPGA to create a 40 MHz clock, but when I checked this clock signal on an oscilloscope it was obviously significantly degraded by slew rate limitations, so it looked more like a sine wave than a square wave. I doubt that it would work to use this signal as a clock to drive the ADC, since the ADC's specifications say the allowable jitter is around 100ps.
I can use an external oscillator to drive the ADC, but then I have to find a way to sync that clock with the 40MHz FPGA clock. Is there any kind of PLL structure that would allow me to sync the myRIO FPGA clock to an external clock? Is there a way to make a single cycle timed loop be driven by an external clock? Or if I was able to customize the FPGA personality to accept an SPI signal of up to 40 MHz (ten times the officially supported limit...), would it be ok to use an FPGA loop running at ~160 MHz and tell it to sample the SPI line each loop and proceed from there?
Thanks!
Solved!
Go to Solution.

Hi 3.14159... ,
The myRIO does not have the ability to import a clock to use on the FPGA Block Diagram to clock single-cycle timed loops (SCTLs). The new sbRIO-9651 that just released at NI Week (not shipping yet) is the only sbRIO that has the ability to import an external clock into LabVIEW. Several of our FlexRIO products also have this ability.
As you alluded to, you can sample the signal at twice the frequency (or possibly more) to and wait until an edge trigger to execute a certain piece of logic. If you open the Example Finder and navigate to Hardware Input and Output » R Series » FPGA Fundamentals » Triggers and Watchdog » Trigger Detection this gives a simple example of doing that. Again, since you are wanting to sample at 10x the supported frequency, all bets are off but it may be worth a try.
Tannerite
National Instruments

Jitter of output digital waveform with external clock

Hi,
I need to generate digital waveform with 20 bits pattern * 1000 times. Digital waveform must be sync with 1 MHz external clock.
It is not big deal.
But there is additional requirement that digital waveform has jitter < 200 ps. It can be delayed for couple ns but it must be very stable.
Can anyone point me on that parameter? Or share your expirience?
Thanks!

Hi Andrei,
Tph on figure 3 is defined as tp - 2.2ns as we discussed earlier. The data jitter, along with channel to channel skew, is already taken into account. We don't specifically spec the data jitter since we have made this calculate for you. It is safe to say that the data jitter involved in tph is less than 200 ps however this is not a standard spec we provide.
As for additional board recommendations, what is your application? The 6562 is designed for LVDS applications. The 655x series is highly recommended for high speed TTL based applications. If you reference the 655x manual you will notice similar or better specifications in regards to setup and hold times, which again already take into account data jitter and skew.
I am curious as to why you would like the specific values documented. We provide the current specifications so that you do not have to use the individual statistics to calculate numerics such as the setup and hold times. Is there something specific you are trying to do here? You mentioned a simple example earlier, what is your actual application?
Regards,
Chris Behnke
Sr. RF Engineer
High Frequency Measurements

Setup external clock

I just bought a GENx192 by lucid. I was having problems with the projectmix and my audio. So I went and picked up a better clock. But now Im wondering how to hook it all up. I have it hooked up I think. But do I have to set the sample rate on both the GENx and in logic or if I have it sync right should I be able to just set the GENx and Logic should change also. Thanks.
I cant remember the name of the cable that I use but its a monster cable and it is the right one thats for sure.

I have an iMac (Intel) running Tiger 10.4.11 and when I have a digital input to this Mac I can see the signal is going in on the input meter in the iMac. But the clock source "default" is greyed out. But it must be clocking to this audiio... I figure... otherwise it would not sync to it. When I remove this input I cannot select external/digital clocking. When I connect a firewire digital audio interface and select properties for it I can select clocking for it either internal or digital.
But my real problem is on a Mac Pro running Leopard 10.5.3. On this Mac it seems to me that I cannot select external or digital clocking under any conditions.
And I am wondering if a change has been from Tiger to Leopard such that there is no option to select digital/external clocking for audio. That is the crux of my question?

How can I use external clock to implement a delay?

Hi all,
I am testing to use external clock to drive dev/PFI0 (on device 6711) which is used as the clock for the analog ouput. I have thinking two applications by using the external clock but I don't have much idea on the implementation yet.
First of all, I have a sequence of data (array) with each sample being sent at the interval of 1us. I use an external clock (10MHz) driving the PFI0 so it is pretty easy to achieve that goal. I am thinking what happen if I want each sampel being sent at different time. For example, if I have 5 samples, I want the first one sent 1us after the task start and wait 2us to send the 2nd sample, wait 5us to send the 3rd sample and wait 11 us to send the 4th sample, and wait 1us to send the last sample. Is it possible to achieve that based on the external clock?
Second question is about the delay. My code require ciritcal timing and the builtin delay doesn't behave very well because I am running in windows. I can increase the priority of the vi to highest, it helps a bit but still not perfect. I am thinking if it is possible to implement hardward delay based on the external clock. Any idea?

Hello dragondriver,
To answer your first question, yes you could send data in that fashion. You would have to programmatically build a pulse train and use that to trigger the sending of data. The answer to the second question is essentially the same. You should be able to programmatically build a pulse train with a delay and use it as trigger to begin whatever operation you have.
Jonathan L.
Applications Engineer
National Instruments

How do I use a quadrature encoder as an external clock (PCI 6229)

Hello, ( a similar post has been placed on DAQ forum apologies as I did not know best place)
I have a PCI 6229 M Series data acquisition card. I want to use a quadrature encoder to be the external clock driving the acquisition of a number of signals. I have set up reading 24 signals each time a clock pulse is received using the DAQ assistant and set my external clock to pin pfi8 (I think) this is then connected to an encoder output. This works well enough until the encoder is run too fast when it appears I am either missing pulses or getting bounce.
How can I set up to clock using a quadrature encoder? I have seen a number of questions on this forum regarding quadrature encoders and reverse counting but not on using them as an external clock.
Basically I want to have the stability and "bounceless" nature of using two outputs from a quadrature encoder whilst still using an external clock. Is this just a case of configuring controls to certain pfi's? If so how is it done?
Any help or pointers would be helpful. So far I have managed very nicely by simply using the DAQ assistant and the interface it has would suggest that if configured for a certain pfi pin I could actually still use it.
Thanks in advance.
Kevin

Hi,
Well I've had alook into this for you and I'm not quite sure I understand what you are looking for.
Is it possible for you to phone back in to support?
The reason you are seeing bounce at high speeds, or indeed loss of points, is due to the sampling rate that you have set up.
What you will find is that the trigger will start an aquisition of a number of points at a certain rate. If your sampling rate is too low then you will not finish that sample batch before the next set of samples is recorded.
It is possible to use an external clock into a trigger or digital line, however this will limit the number of samples you can take to the speed of your encoder.
If you increase your sampling rates, and then configure a start trigger from a single input from the encoder you will be able to record a number of samples after a rising/falling edge. (Set the clock as an internal clock)
Hope this helps
AdamB
Applications Engineering Team Leader | National Instruments | UK & Ireland

Is the PXIe-PCIe8361 adequate for this system? And external clock questions...

Hi all,
I have spent some time piecing together a system and I'd like a sanity check before pulling the trigger on this purchase. The system will contain the following hardware:
1. Chassis: PXIe-1078
2. Controller: PXIe-PCIe8361
3. 3 x PXIe-6363 (16 analog inputs each card, 32 digital inputs each card, all internally clocked @ 10kHz)
4. 2 x PXI-6224 (32 digital inputs on one, 8 digital inputs on the other, externally clocked in "bursts" of 62.5khz)
5. Labview software
The three PXI-6363 cards will be responsible for a mix of analog and digital measurements made @ 10 kHz, timed continuously by the onboard clock.
One PXI-6224 will be clocked externally @ 62.5 kHz and will be used to collect digital data on a 32-bit port. These clock pulses will not be continuous, but will occur in bursts lasting for 2ms every 20ms.
The other PXI-6224 will be clocked externally @ 62.5kHz as well and will be used to collect digital data on an 8-bit port. These clock pulses will not be continuous, but will occur in bursts lasting for 2 ms at random intervals.
My questions are:
1. Am I planning anything that looks unreasonable for this hardware?
2. Should I expect issues with data transfer rates with the PXIe-PCIe8361? I will be operating well within the advertised 110MB/s throughput of the device. I plan to stream this method... NI Fast TDMS data streaming
3. I have only ever used NI cards for continuous measurements made by an onboard clock. When I set up a task to collect data that is externally-timed, will the DAQ be expecting a "continuous" clock pulse, or will the system wait patiently for clock pulses to arrive at any rate (any rate within the spec of the card, of course)?
Thanks, any input is appreciated.

Hello LucasH0011
1-As long as you put the PXI-6224 and the PXIe-6363 cards in the corresponding slots, meaning the express(PXIe-6363) in the express and the hybrid(PXI-6224) in the hybrid.
2-I think you would not have issues with the transfer rate.
3-Your timing specifications sound reasonable to me, I think you will be fine.
Here is a document that has useful concepts for the use of cards:
http://www.ni.com/white-paper/3615/en/
It is for the M-Series, but the concepts apply to the X-Series as well.
Regards
Ernesto

ASYNC to SYNC scenario using BPM.

hi,
i have a async to sync scenario. i have a File sender->PI(BPM)->ECC and the response from ECC->PI->SOAP.
Here in PI, i am using BPM. The ECC side is a Synchronous BAPI. The response is sent to the SOAP receiver.
in BPM, can someone tell me how many transformation steps do i need i.e mappings. and how many abstract interfaces, synchronous interfaces, outbound interfaces, inbound interfaces?
also how many send,receive and transformation steps.
and in the configuration part,
how many receiver determinations, interface determinations do we need.
rgds,
mithun

Hi,
File sender->PI(BPM)->ECC and the response from ECC->PI->SOAP
Service interfaces
-> SI_OB for file (Request)
->SI_IB for Soap(ASy Response)
->SI_ABstract(ASy Request)
->SI_Abstract (Asy Response)
->Si_REq_RES_ABS(Syn)
->SI_ABS(ASY BAPI REQ)
->SI_ABS(ASY BAPI RES)
mappings
one for request mapping(file Req to BAPREQ) and one for response mapping(BAPI REs to RESponse mSg).
operation mappings-2, one for Req MApping ANd One for Res ponse mapping.
IP
reciv->transformation(REq)->Send(SYN/ASYN)->transformation(RES)->Send
ID:
3 reciver deteminations
one for file to IP
IP to ECC and IP to SOAP
3 interface determinations
1 sender agrement
2 reciver sgrements
one for IP to ECC
and IP to SOAPregards,
ganesh

Doc on Async and Sync using BPM

Hi all
Can anyone send some docs explaining the steps involved in bridging async and sync interface using BPM. The source adapter is JDBC and target is proxy. I've already checked one blog by krishna moorthy (File-File using BPM) and based on that i tried but coudnt get the expected result for my scenario.
Thkx

Hi PS,
in your Integration Repository go to:
Software Component: SAP BASIS
Namespace: http://sap.com/xi/XI/System/Patterns
Process: BpmPatternSyncAsyncBridge
This is a very good example!
Regards Mario

Async to Sync Scenario

Hi Experts,
I am doing async JDBC to sync webservice scenario.
I did create async interface for JDBC and sync interface for webservice.
my scenario is i just want to see the response from webservice in XI for trouble shoot, i dont need to send the response message to database.
can anyone tell me how can we do it without using BPM (async to sync bridge).
Kind Regards,
kiran

Hi
Please go through below steps now
I have added the comments with same in bold font
Data Types: JDBC_DT,File_DT
Message Types: JDBC_MT,File_MT
Message Interfaces:
JDBC_OUT_MI(outbound,async),This should be Sync given MT_File as respo
File_MI(inbound,async), Dont use this
WS_IN_MI(inbound,sync,input=WS_req,output=WS_resp)
WS_resp_MI(outbound,async,WS_resp), -----No need of this
Message Mappings:
JDBC_WS_req_MM
(JDBC_OUT(JDBC_MT)------->WS_IN_MI(WS_req) ).
*Here WS_IN_MM msg. mapping should be used insted of*
*WS_IN_MI i.e message interface*
*WS_File_Res_MM*
(WS_Res(Source -- Ws_res) ---> File_MT)
Interface Mapping: JDBC_WS_req_IM(source=JDBC_OUT_MI,target=WS_IN_MI)
In IM you need to use the above one only
Here you have two tabs as Request & Response, Request will be normal as
it is JDBC_MT to WS_Req with proper mapping
*In Response use File_MT <--- Ws_RES with appropriate mapping *
For ID configuration refer below sample scenario,
It is File1 to RFC to File2- Just in your scenario it is JDBC>WS--->File2
So refer and do necessary changes
From SP 19 on XI 3.0 and SP 10 on PI 7.0, a File - RFC - File ( Asynch - Synch ) scenario can be done without a BPM.
Steps:
Integration Repository
The Integration Repository will be similar to any Synchronous Scenario ( say HTTP - RFC ) . 1 Outbound Synch message Interface and 1 Inbound Synch Message Interface.
Integration Directory
This is where a few differences lie, so let me take some time.
1. The Receiver Determination , Interface Determination will be the same as in HTTP - RFC synch scenario. Create the Sender File Adapter, Receiver RFC Adapter and Receiver File Adapter.
2. Sender Agreement will be for the Sender File Adapter. Sender Agreement uses the Synch Outbound Message Interface.
3. Receiver Agreement will be for the Receiver RFC adapter. Receievr Agreement will use the RFC as thge Inbound Message Interface.
4. We need to add a few modules in the Sender File Adapter.
Go to the Modules Tab of the Sender File Adater, and add the following modules in the same sequence,
Number - ModuleName - Type - ModuleKey
code1- AF_Modules/RequestResponseBean - Local Enterprise Bean - 1
2- CallSapAdapter-Local Enterprise Bean - 2
3-AF_Modules/ResponseOnewayBean-3[/code]
Parameters
ModuleKey - ParameterName - ParameterValue
code1 - passThrough - true
3-receiverChannel - Receiver File Adapter Name
3-receiverService - Receiver Business Service/ System[/code]
With this configuration, you can now handle the requirement without a BPM
This feature been already blogged for JMS Adapters in these blogs ,
Sync/Async communication in JMS adapter without BPM (SP19)
/people/venkataramanan.parameswaran/blog/2007/01/18/syncasync-communication-in-jms-adapter-without-bpm-sp19
Async/Sync Communication using JMS adapter without BPM (SP 19)
/people/sudheer.babu2/blog/2007/01/18/asyncsync-communication-using-jms-adapter-without-bpm-sp-19
Dynamic Configuration is also possible,and this as well as many other options are discussed in the How To guide - "How To Realize a sync-async and async-sync
bridge within the Adapter Framework" available on the Service Market Place.
For info on the Modules used here, look into these links,
Request Response Bean
http://help.sap.com/saphelp_nw04/helpdata/en/45/20c210c20a0732e10000000a155369/content.htm
Response Oneway Bean
http://help.sap.com/saphelp_nw04/helpdata/en/45/20cc5dc2180733e10000000a155369/content.htm
Hope this info helps,
Thanks
Swarup

Converting async to sync nrz external clock

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