Luupgrade from ufs to zfs on a Sun Fire E6900

I'm going to put the error right up front and then list the events surrounding it.
Mounting root on rpool/ROOT/sol10_u10 with filesystem type zfs is not supported
^@panic[cpu0]/thread=180e000: vfs_mountroot: cannot remount root
000000000180b950 genunix:vfs_mountroot+398 (600564c9540, 19c9d98, 19edd00, 1a14000, 1a1c400, 19c4940)
  %l0-3: 00000600564c9540 0000000001291400 00000000019c43d8 00000600564c9540
  %l4-7: 00000000019edd00 0000000000002420 0000000000000420 0000000000002000
000000000180ba10 genunix:main+104 (1a13400, 180c000, 18cd040, 10a7000, 0, 18ceec8) 
%l0-3: 0000000000000001 0000000070002000 0000000070002000 0000000000000000
  %l4-7: 0000000001955400 0000000000000000 0000000001836000 00000000018360f8
I am trying to upgrade a Sun Fire E6900 from Sol10-u6 ufs to Sol10-u10 zfs.
The system is running on SVM mirrored disks, with partitions for 2 BE's.
metastat -c
d600             m   19GB d601 d602
    d601         s   19GB c0t6d0s5
    d602         s   19GB c1t0d0s5
d500             m   10GB d501 d502
    d501         s   10GB c0t6d0s4
    d502         s   10GB c1t0d0s4
d400             m   19GB d401 d402
    d401         s   19GB c0t6d0s3
    d402         s   19GB c1t0d0s3
d200             m   10GB d201 d202
    d201         s   10GB c0t6d0s1
    d202         s   10GB c1t0d0s1
d100             m   10GB d101 d102
    d101         s   10GB c0t6d0s0
    d102         s   10GB c1t0d0s0
I have a separate disk for the zfs BE, so there is no need  to break the mirror.
zpool statusE
  pool: rpool
status: The pool is formatted using an older on-disk format.  T
he pool can still be used, but some features are unavailable.
action: Upgrade the pool using 'zpool upgrade'.  Once this is done,
the pool will no longer be accessible on older software versions.
scan: none requested config:
        NAME        STATE     READ WRITE CKSUM
       rpool       ONLINE       0     0     0
         c1t6d0s0  ONLINE       0     0     0
I have created a new BE and luupgraded it to Sol10-u10. I activated and booted to this BE.
lustatus
Boot Environment           Is       Active Active    Can    Copy
Name                       Complete Now    On Reboot Delete Status
sol10_u6                   yes      no     no        yes    -
sol10_u10_tmp              yes      yes    yes       no     -
I then lucreated the Sol10-u10 zfs BE
lucreate -s sol10_u10_tmp -n sol10_u10 -p rpool
NAME                   USED  AVAIL  REFER  MOUNTPOINT
rpool                      24.5G  42.5G    18K  /rpool
rpool/ROOT            12.1G  42.5G    19K  legacy
rpool/ROOT/sol10_u10  12.1G  42.5G  12.1G  /
rpool/dump            2.06G  44.5G    16K  -
rpool/swap            10.3G  52.8G    16K  -
I got the above error on reboot.
I booted to the sol10_u10_tmp (ufs) BE, and did these commands:
zpool upgrade rpool  (now on version 29)
zpool set bootfs=rpool/ROOT/opensolaris rpool
installboot -F zfs /usr/platform/sun4u/lib/fs/zfs/bootblk /dev/rdsk/c1t6d0s0
I am still getting the above error.
Thanks for your consideration;
Dave

Hi Dave,
I'll have to guess at this point and back track a bit:
1. Does this system have up-to-date firmware?
2. Did you apply the current LU patch set to the s10u6 boot environment?
3. The system should have booted when you activated the s10u10 BE,
but I see an error in your zpool set bootfs command. It should be:
zpool set bootfs=rpool/ROOT/sol10_u10_tmp rpool
Thanks, Cindy

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    *0>IO-Bridge unit 0 init test*
    *0>IO-Bridge unit 1 init test*
    *0>Do PLL reset*
    *0>Setting timing to 8:1 10:1, system frequency 160 MHz, CPU frequency 1280 MHz*
    *0>Soft Power-on RST thru SW*
    *0>CPUs present in system: 0 1*
    +*0>*+
    *0>Resume selftest...*
    *0>Init SB*
    *0>Init CPU*
    *0>Init mmu regs*
    *0>Setup L2 Cache*
    *0>L2 Cache Control = 00000000.00f04400*
    *0>     Size = 00000000.00100000...*
    *0>Setup and Enable DMMU*
    *0>Setup DMMU Miss Handler*
    *0>Timing is 8:1 10:1, sys 159 MHz, CPU 1279 MHz, mem 127 MHz.*
    +*0>     UltraSPARC[TM] IIIi, Version 2.4*+
    *1>Init CPU*
    +*1>     UltraSPARC[TM] IIIi, Version 2.4*+
    *1>Init mmu regs*
    *1>Setup L2 Cache*
    *1>L2 Cache Control = 00000000.00f04400*
    *1>     Size = 00000000.00100000...*
    *1>Setup and Enable DMMU*
    *1>Setup DMMU Miss Handler*
    *1>Timing is 8:1 10:1, sys 159 MHz, CPU 1279 MHz, mem 127 MHz.*
    *0>Initialize I2C Controller*
    *1>Init Mem Controller Sequence*
    *0>Init Mem Controller Sequence*
    *0>IO-Bridge unit 0 init test*
    *0>IO-Bridge unit 1 init test*
    *0>Select Bank Config*
    *0>Probe and Setup Memory*
    *0>INFO:     1024MB Bank 0, Dimm Type X4*
    *0>INFO:     1024MB Bank 1, Dimm Type X4*
    *0>INFO:     No memory detected in Bank 2*
    *0>INFO:     No memory detected in Bank 3*
    +*0>*+
    *0>Data Bitwalk on Master*
    *0>     Test Bank 0.*
    +*0>*+
    *0>ERROR: TEST = Data Bitwalk on Master*
    *0>H/W under test = CPU0: Bank0 DIMM0, Motherboard*
    *0>Repair Instructions: Replace items in order listed by 'H/W under test' above*
    *0>MSG = Pin 79 failed on CPU0: Bank0 DIMM0, Motherboard*
    *0>END_ERROR*
    *0>     Test Bank 1.*
    +*0>*+
    *0>ERROR: TEST = Data Bitwalk on Master*
    *0>H/W under test = CPU0: Bank1 DIMM0, Motherboard*
    *0>Repair Instructions: Replace items in order listed by 'H/W under test' above*
    *0>MSG = Pin 79 failed on CPU0: Bank1 DIMM0, Motherboard*
    *0>END_ERROR*
    +*0>*+
    *0>ERROR: TEST = Data Bitwalk on Master*
    *0>H/W under test = CPU, Memory, Motherboard*
    *0>Repair Instructions: Replace items in order listed by 'H/W under test' above*
    *0>MSG =*
    *      *** Test Failed!! ****
    *0>END_ERROR*
    +*0>*+
    *0>ERROR: TEST = Data Bitwalk on Master*
    *0>H/W under test = CPU, Memory, Motherboard*
    *0>Repair Instructions: Replace items in order listed by 'H/W under test' above*
    *0>MSG = No good memory available on master CPU 0, rolling over to new Master.*
    *0>END_ERROR*
    *1>Soft Power-on RST thru SW*
    *1>CPUs present in system: 0 1*
    *1>OBP->POST Call with %o0=00000000.05002000.*
    *1>Diag level set to MIN.*
    *1>MFG scrpt mode set to NONE*
    *1>I/O port set to TTYA.*
    +*1>*+
    *1>Start selftest...*
    *1>Init SB*
    *1>Init CPU*
    *1>DMMU*
    *1>DMMU TLB DATA RAM Access*
    *1>DMMU TLB TAGS Access*
    *1>IMMU Registers Access*
    *1>IMMU TLB DATA RAM Access*
    *1>IMMU TLB TAGS Access*
    *1>Init mmu regs*
    *1>Setup L2 Cache*
    *1>L2 Cache Control = 00000000.00f04400*
    *1>     Size = 00000000.00100000...*
    *1>Scrub and Setup L2 Cache*
    *1>Setup and Enable DMMU*
    *1>Setup DMMU Miss Handler*
    *1>Test and Init Temp Mailbox*
    *1>CPU Tick and Tick Compare Registers Test*
    *1>CPU Stick and Stick Compare Registers Test*
    *1>Set Timing*
    +*1>     UltraSPARC[TM] IIIi, Version 2.4*+
    *0>Init CPU*
    +*0>     UltraSPARC[TM] IIIi, Version 2.4*+
    *0>DMMU*
    *0>DMMU TLB DATA RAM Access*
    *0>DMMU TLB TAGS Access*
    *0>IMMU Registers Access*
    *0>IMMU TLB DATA RAM Access*
    *0>IMMU TLB TAGS Access*
    *0>Init mmu regs*
    *0>Setup L2 Cache*
    *0>L2 Cache Control = 00000000.00f04400*
    *0>     Size = 00000000.00100000...*
    *0>Scrub and Setup L2 Cache*
    *0>Setup and Enable DMMU*
    *0>Setup DMMU Miss Handler*
    *0>Test and Init Temp Mailbox*
    *0>CPU Tick and Tick Compare Registers Test*
    *0>CPU Stick and Stick Compare Registers Test*
    *0>Setup Int Handlers*
    *1>Setup Int Handlers*
    *1>Send Int CPU 0*
    *0>Send Int to Master CPU*
    *1>Initialize I2C Controller*
    *1>MB:     Part-Dash-Rev#:  3753130-02-50     Serial#:  020322*
    *1>Set CPU/System Speed*
    *1>MCR Timing index = 00000000.00000002*
    *1>..*
    *1>Send MC Timing CPU 0*
    *1>Probe Dimms*
    *0>Probe Dimms*
    *0>Init Mem Controller Regs*
    *1>Init Mem Controller Regs*
    *0>Set JBUS config reg*
    *1>Set JBUS config reg*
    *1>IO-Bridge unit 0 init test*
    *1>IO-Bridge unit 1 init test*
    *1>Do PLL reset*
    *1>Setting timing to 8:1 10:1, system frequency 160 MHz, CPU frequency 1280 MHz*
    *1>Soft Power-on RST thru SW*
    *1>CPUs present in system: 0 1*
    +*1>*+
    *1>Resume selftest...*
    *1>Init SB*
    *1>Init CPU*
    *1>Init mmu regs*
    *1>Setup L2 Cache*
    *1>L2 Cache Control = 00000000.00f04400*
    *1>     Size = 00000000.00100000...*
    *1>Setup and Enable DMMU*
    *1>Setup DMMU Miss Handler*
    *1>Timing is 8:1 10:1, sys 159 MHz, CPU 1279 MHz, mem 127 MHz.*
    +*1>     UltraSPARC[TM] IIIi, Version 2.4*+
    *0>Init CPU*
    +*0>     UltraSPARC[TM] IIIi, Version 2.4*+
    *0>Init mmu regs*
    *0>Setup L2 Cache*
    *0>L2 Cache Control = 00000000.00f04400*
    *0>     Size = 00000000.00100000...*
    *0>Setup and Enable DMMU*
    *0>Setup DMMU Miss Handler*
    *0>Timing is 8:1 10:1, sys 159 MHz, CPU 1279 MHz, mem 127 MHz.*
    *1>Initialize I2C Controller*
    *0>Init Mem Controller Sequence*
    *1>Init Mem Controller Sequence*
    *1>IO-Bridge unit 0 init test*
    *1>IO-Bridge unit 1 init test*
    *1>Select Bank Config*
    *1>Probe and Setup Memory*
    *1>INFO: No memory on cpu 1*
    +*1>*+
    *1>ERROR: TEST = Probe and Setup Memory*
    *1>H/W under test = CPU1 Memory*
    *1>Repair Instructions: Replace items in order listed by 'H/W under test' above*
    *1>MSG = No good memory available on master CPU 1, rolling over to new Master.*
    *1>END_ERROR*
    *1>ERROR:*
    *1>     POST toplevel status has the following failures:*
    *1>          CPU0: Bank0 DIMM0, Motherboard*
    *1>          CPU0: Bank1 DIMM0, Motherboard*
    *1>END_ERROR*
    +*1>*+
    *1>ERROR:     No good CPUs OR CPUs with good memory left.  Calling debug menu.*
    *1>     0     Peek/Poke interface*
    *1>     1     Dump CPU Regs*
    *1>     2     Dump Mem Controller Regs*
    *1>     3     Dump Valid DMMU entries*
    *1>     4     Dump IMMU entries*
    *1>     5     Dump Mailbox*
    *1>     6     Dump IO-Bridge regs unit 0*
    *1>     7     Dump IO-Bridge regs unit 1*
    *1>     8     Allow other CPUs to print*
    *1>     9     Do soft reset*
    *1>     ?     Help*

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