Sampling rate of onboard ADC of spartan 3e

hello
I am doing a project on FIR filters. For filtering data , i need to convert it into digital form. I am using the onboard ADC of Spartan 3e.Plz tell how can i change the sampling frequency of the onboard ADC? what really controls the sampling frequency of ADC. I know its very unlikey to go beyond the maximum 1.5Mhz per channel, but i can reduce the sampling frequency of the ADC? I have read the datasheet but i couldnt find it...Please help me here and alos tell me under what conditions we can have maximum frequecny.And if anybody can share its code in Verilog it will be huge help...
Thanks

The Spartan 3E doesn't have a built-in ADC. Are you using a particular Spartan 3E development board that has a separate ADC chip? If so, you should refer to the board's data sheet and/or schematics to see how the clock is generated and whether this clock is programmable.

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Hey Tori,
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Join / Follow the LabVIEW Hacker Group on google+

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Sample rate off the audio input and out devices do not match - what to do?

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Sampling rate of onboard ADC of spartan 3e

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