Split Int into bits in LabVIEW FPGA

Is there a clever way of splitting an Uint32 into 32 directly accessable bits (not an aray) in LabVIEW FPGA?
The only way I could come up with is the following, which is a pain write for 32bits, and seems kind of a waste og resources to store all these indexes.
Regards, mola
Solved!
Go to Solution.

I figured it out. I could use clusters by right-clicking the Array to Cluster block and increase the cluster size to 32.

Similar Messages

How to import Verilog codes into LabVIEW FPGA?

I tried to import Verilog code by instantiation followed by the instruction in http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3,
but still I can see some errors while compiling the VI file.
Simple test Verilog file is as follows:
==============================
module andtwobits (xx, yy, zz);
input xx, yy;
output reg zz;
always @(xx,yy) begin
zz <= xx & yy;
end
endmodule
==============================
and after following up the above link, we created the instantiation file as
==============================================
library ieee;
use ieee.std_logic_1164.all;
entity mainVHDL is
port(
xxin: in std_logic;
yyin: in std_logic;
zzout: out std_logic
end mainVHDL;
architecture mainVHDL1 of mainVHDL is
COMPONENT andtwobits PORT (
zz : out std_logic;
xx : in std_logic;
yy : in std_logic);
END COMPONENT;
begin
alu : andtwobits port map(
zz => zzout,
xx => xxin,
yy => yyin);
end mainVHDL1;
==============================================
Sometimes, we observe the following error when we put the indicator on the output port,
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq_ms*" TNM =
TNM_ChinchIrq_IpIrq_ms;> [Puma20Top.ucf(890)]: INST
"*ChinchLvFpgaIrq*bIpIrq_ms*" does not match any design objects.
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq*" TNM =
TNM_ChinchIrq_IpIrq;> [Puma20Top.ucf(891)]: INST "*ChinchLvFpgaIrq*bIpIrq*"
does not match any design objects.
and interestingly, if we remove the indicator from the output port, it sucessfully compiles on the LabVIEW FPGA.
Could you take a look at and please help me to import Verilog to LabVIEW FPGA?
I've followed the basic steps of instantiation on the above link, but still it won't work.
Please find the attachment for the all files.
- andtwobits.v : original Verilog file
- andtwobits.ngc: NGC file
- andtwobits.vhd: VHD file after post-translate simulation model
- mainVHDL.vhd: instantiation main file
Since there is no example file for Verilog (there is VHDL file, but not for Verilog), it is a bit hard to do the simple execution on LabVIEW FPGA even for the examples.
Thank you very much for your support, and I'm looking forward to seeing your any help/reply as soon as possible.
Bests,
Solved!
Go to Solution.
Attachments:
attach.zip ‏57 KB

Hi,
I am facing problem in creating successfully importing VHDL wrapper file for a Verilog module,into LabVIEW FPGA using CLIP Node method. Please note that:
I am working on platform SbRIO-9606.
Labiew version used is 2011 with Xilinx 12.4 compiler tools
NI RIO 4.0 is installed
Xilinx ISE version installed in PC is also 12.4 webpack ( Though I used before Xilinx 10.1 in PC for generating .ngc file for verilog code FOR SbRIO 9642 platform, but problem remains same for both versions)
Query1. Which versions of Xilinx ISE (to be installed in PC for generating .ngc file) are compatible with Labview 2011.1(with Xilinx 12.4 Compiler tools)? Can any version be used up to 12.4?
Initially I took a basic and gate verilog example to import into LabVIEW FPGA i.e. simple_and.v and its corresponding VHDL file is SimpleAnd_Wrapper.vhd
///////////////// Verilog code of “simple_and.v”//////////////////////
module simple_and(in1, in2, out1);
   input in1,in2;
   output reg out1;
   always@( in1 or in2)
   begin
      out1 <= in1 & in2;
   end
endmodule
/////////////////VHDL Wrapper file code of “SimpleAnd_Wrapper.vhd” //////////////////////
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SimpleAnd_Wrapper IS
    port (
        in1    : in std_logic;
        in2    : in std_logic;
        out1   : out std_logic
END SimpleAnd_Wrapper;
ARCHITECTURE RTL of SimpleAnd_Wrapper IS
component simple_and
   port(
         in1    : in std_logic;
         in2    : in std_logic;
         out1   : out std_logic
end component;
BEGIN
simple_and_instant: simple_and
   port map(
            in1 => in1,
            in2 => in2,
            out1 => out1
END RTL;
Documents/tutorials followed for generating VHDL Wrapper file for Verilog core are:
NI tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. Link is http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3
In this case, I did not get any vhdl file after “post-translate simulation model step” in netlist project using simple_and.ngc file previously generated through XST. Instead I got was simple_and_translate.v.
Query2. Do I hv to name tht “v” file into “simple_and.vhd”?? Anyways it did not work both ways i.e. naming it as “simple_and with a “v” or “vhd” extension. In end I copied that “simple_and.v” post translate model file, “simple_and.ngc”, and VHDL Wrapper file “SimpleAnd_Wrapper.vhd” in the respective labview project directory.
Query3. The post-translate model file can also be generated by implementing verilog simple_and.v file, so why have to generate it by making a separate netlist project using “simple_and.ngc” file? Is there any difference between these two files simple_and_translate.v generated through separate approaches as I mentioned?
2. NI tutorial “Using Verilog Modules in a Component-Level IP Design”. Link is https://decibel.ni.com/content/docs/DOC-8218.
In this case, I generated only “simple_and.ngc” file by synthesizing “simple_and.v “file using Xilinx ISE 12.4 tool. Copied that “simple_and.ngc” and “SimpleAnd_Wrapper.vhd” file in the same directory.
Query4. What is the difference between this method and the above one?
2. I followed tutorial “Importing External IP into LABVIEW FPGA” for rest steps of creating a CLIP, declaring it and passing data between CLIP and FPGA VI. Link is http://www.ni.com/white-paper/7444/en. This VI executes perfectly on FPGA for the example”simple_and.vhd” file being provided in this tutorial.
Compilation Errors Warnings received after compiling my SimpleAnd_Wrapper.vhd file
Elaborating entity <SimpleAnd_Wrapper> (architecture <RTL>) from library <work>.
WARNING:HDLCompiler:89"\NIFPGA\jobs\WcD1f16_fqu2nOv\SimpleAnd_Wrapper.vhd"    Line 35: <simple_and> remains a black-box since it has no binding entity.
2. WARNING:NgdBuild:604 - logical block 'window/theCLIPs/Component_ dash_Level _IP_ CLIP0/simple_and_instant' with type   'simple_and' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'simple_and' is not supported in target 'spartan6'.
3. ERROR:MapLib:979 - LUT6 symbol   "window/theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainInd icator/cQ_0_rstpot" (output signal=window/theVI/ Component_dash_Level _IP_bksl_out1_ ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot) has input signal "window/internal_Component_dash_Level_IP_out1" which will be trimmed. SeeSection 5 of the Map Report File for details about why the input signal willbecome undriven.
Query5. Where lays that “section5” of map report? It maybe a ridiculous question, but sorry I really can’t find it; maybe it lays in xilnx log file!
4. ERROR:MapLib:978 - LUT6 symbol "window/theVI/Component_dash_Level_IP_bksl_ out1_ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot" (output signal= window / theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainIndicator/ cQ_0_rstpot) has an equation that uses input pin I5, which no longer has a connected signal. Please ensure that all the pins used in the equation for this LUT have signals that are not trimmed (see Section 5 of the Map Report File for details on which signals were trimmed). Error found in mapping process, exiting.Errors found during the mapping phase. Please see map report file for more details. Output files will not be written.
Seeing these errors I have reached the following conclusions.
There is some problem in making that VHDL Wrapper file, LabVIEW does not recognize the Verilog component instantiated in it and treat it as unresolved black box.
Query6. Is there any step I maybe missing while making this VHDL wrapper file; in my opinion I have tried every possibility in docs/help available in NI forums?
2. Query7. Maybe it is a pure Xilinx issue i.e. some sort of library conflict as verilog module is not binding to top VHDL module as can be seen from warning HDLCompiler89. If this is the case then how to resolve that library conflict? Some hint regarding this expected issue has been given in point 7 of tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3. But nothing has been said much about resolving that issue.
3. Because of this unidentified black box, the whole design could not be mapped and hence could not be compiled.
P.S.
I have attached labview project zip folder containing simple_translate.v, simple_and_verilog.vi file,SimpleAnd_Wrapper.xml, Xilinx log file after compilation alongwith other files. Kindly analyze and help me out in resolving this basic issue.
Please note that I have made all settings regarding:
Unchecked add I/O buffers option in XST of Xilinx ISE 12.4 project
Have set “Pack I/O Registers into IOBs” to NO in XST properties of project.
Synchronization registers are also set to zero by default of all CLIP I/O terminals.
Please I need speedy help.Thanking in you in anticipation.
Attachments:
XilinxLog.txt ‏256 KB
labview project files.zip ‏51 KB

How do I install Labview 64 bit support for the labview fpga module?

see subject.

Hi,
The LabVIEW FPGA Module uses the 32-bit version of the Xilinx tools, even on the 64-bit OS.
There is no 64 bit version of LabVIEW FPGA and you must have LabVIEW 32 bit
installed on your 64-bit machine to use the compatible version of
LabVIEW FPGA.
NI LabVIEW FPGA Module will run within the 32-bit emulation layer, Windows on Windows (WOW64).
regards,
Houssam Kassri
NI Germany

FlexRIO DRAM problem in Labview FPGA 2010

Hello,
I am just switching from Labview FPGA 2009 to Labview FPGA 2010 and I am having compilation problems with very simple projects that shouldn't fail to compile.
I am using a FlexRIO 7965R board as a target. Initially, I just wanted to recompile a project that was working fine under Labview FPGA 2009. When it failed, I drastically
simplified it to isolate the source of error. I ended up with what is attached. In this very simple VI I just write some values into DRAM banks in one timed loop, read them out in another and send them through a Target to Host DMA FIFO. Both loops are quite slow running at only 40 MHz. Previously, I was able to compile VIs with DRAM clip nodes in timed loops running at 100 MHz without any problems.
The compilation fails with this summary:
"Compilation
failed due to resource overmapping"
although it should fit easily.
The error is definitely related to DRAM. This s what Xilinx log says:
"ERRORlace:543
- This design does not fit into the number of slices available in this device
due to the complexity of
   the design and/or constraints.
   Unplaced instances by type:
     IDELAYCTRL    21 (48.8) "
Then it lists these instances (about 20):
   0. IDELAYCTRL
Puma20DramMainx/GenBank0or1Mig.u_ddr2_idelay_ctrl/u_idelayctrl_MapLib_replicate0
   1. IDELAYCTRL
Puma20DramMainx/GenBank0or1Mig.u_ddr2_idelay_ctrl/u_idelayctrl_MapLib_replicate1
   2. IDELAYCTRL Puma20DramMainx/GenBank0or1Mig.u_ddr2_idelay_ctrl/u_idelayctrl_MapLib_replicate2
Both DRAM banks are configured with the clip node for 128-bit FIFO version v1.1.0. I also tried using the legacy version v1.0.0 but it didn't make any difference.
It looks like I have some configuration problems I can't identify or there is something wrong with the DRAM clip node in Labview FPGA 2010.
Any ideas on what could be happening here? Any help would be much appreciated.
Regards,
Ivan
Attachments:
flexrio_dram_test.lvproj ‏157 KB
flexrio_dram_test_fpga.vi ‏124 KB

Hello Ivan,
It looks like in your project you are using both the NI 5761 adapter module and DRAM. We have seen a few cases where certain combinations of DRAM, adapter modules, and FlexRIO FPGA targets in LabVIEW FPGA 2010 have caused some resource overmapping errors of the IODelayCtrl components used in the adapter module and DRAM CLIPs. Due to a bug, certain constraints inside of the CLIP cores are misinterpreted by the ISE compiler causing this overmap error when you switch to LabVIEW FPGA 2010.
This was reported to R&D (# 258076) for further investigation and to create a long term fix. In the meantime, for this specific issue please use the following knowledgebase article to apply a patch to your FlexRIO fixed logic files. This patch updates some of the constraints used by the DRAM to ensure that the Xilinx compiler can properly interpret them. There are more details on your issue in the knowledgebase as well.
Knowledgebase 5E4FNCDP: Error, “Compilation Failed Due to Resource Overmapping,” When Using NI FlexR...
If you do run into any other issues regarding IODelayCtrl components, feel free to reply to this forum topic to let me know about them.
Regards,
Browning G
FlexRIO R&D

Threshold and interpolate array in LabVIEW FPGA

Hi,
It's a classical one, but I don't find an answer that fit my problem :
I want to threshold an array with a 4-20 mA analog input then interpolate an other array with the result of the threshold.
The result of the interpolation is then sent to an 4-20 mA analog output.
Very simple ! Just like that :
But I want to do that in LabVIEW FPGA on a cRIO 9074....and these functions don't exist in LabVIEW FPGA.
I failed to use LUT, so I need some help...
The 4-20 mA modules give/need a single-precision floating point format.
Thanks,

I have already told you the solution: use the lookup table Express VI (which is implemented as a memory block). Why does this not work for you?
The lookup table express VI includes interpolation. There is no need for thresholding. In fact, in your original example, there is also no need for thresholding. You can combine the two arrays into an array of 2-element clusters, which makes it effectively a lookup table, and wire that to the interpolate function alone.
If you have enough RAM available on the FPGA, you can also avoid interpolation by creating a lookup table large enough to hold every possible input value (and corresponding output). Since you are dealing with a 16-bit input, there are only 65536 possible values. I realized I provided the wrong numbers in my earlier post (I was off by a factor of 2). The address is the input and the table contains the corresponding outputs, so your lookup table will consume only 65536 * 2 = 131072 bytes or 128kb of RAM (each output value is 16 bits or 2 bytes).
I don't have the LabVIEW 2013 FPGA module available right now, and I can't find any documentation suggesting that the inputs and outputs are single-precision floating point values. Everything I see says that they are fixed-point values. Are you sure that the inputs and outputs are floating point? Can you provide a screenshot? In any case, regardless of the numeric format, you are limited by the 16-bit precision of the inputs and outputs, so you'll never have more than those 65536 possible values. If you do have to do the conversion, you can use the To Fixed Point and Fixed Point to Integer Cast functions (and the equivalents in the reverse direction). That will give you an integer with the same bit pattern as the fixed-point equivalent which you can use as an integer input to the lookup table.

RS 422 @ 8Mbit/s is it possible with Labview FPGA??

Hi,
I've to read and write data over an RS422 link at a rate of 8Mbit/s.
Do you think it's possible to implement RS422 @8Mbit/s with labview FPGA?
I know that I will have to make electrical adaptation to use RS422 signals with FPGA card.
Can the FPGA IP available on this website do this?
Thanks a lot
Julesjay

Christophe wrote "Yes it's possible to implement this into FPGA, if you adapt the electrical signal."
Are you sure ?
Depending on if that spec is baud vs bit rate and the over-sampling implemented in most serial read logic, the FPGA may not be able to cycle fast enough.
Ben
Ben Rayner
I am currently active on.. MainStream Preppers
Rayner's Ridge is under construction

HELP -FPGA SPARTAN 3E-100 CP132 WORKS WITH LABVIEW FPGA ?

HI EVERYBODY, IM TRYING TO USE MY FPGA BOARD WITH LABVIEW, BUT I DONT KNOW THAT IF ITS COMPATIBLE, I INSTALLED DRIVERS, FPGA MODULE, AND LABVIEW 2012, IM USING WINDOWS 7 32 BITS, AND AFTER I COMPILE ITS SAID :
LabVIEW FPGA called another software component, and that component returned the following error:
Error Code: -310601
NI-COBS: Unable to detect communication cable.
Please verify that the communication cable is plugged securely into your computer and target. Also verify that the appropriate drivers are installed.
THANK YOU .
=)
Solved!
Go to Solution.

Hi dvaldez2.
LabVIEW FPGA does not offer support for any third party hardware, other than the Spartan 3E XUP Starter Kit. Those are probably the drivers you downloaded.
http://digital.ni.com/express.nsf/bycode/spartan3e?opendocument&lang=en&node=seminar_US
However, this driver only supports the Starter Kit board itself (http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,790&Prod=S3EBOARD). You can't use the driver with any other FPGA from Xilinx.
Hope this helps.
Aldo H
Ingenieria de Aplicaciones

How do I file Bug Report? Labview FPGA

I'm not sure if this is a software bug or what, but I'm trying to run the Analog Input example project for Labview FPGA , in "Find Examples >> Hardware Input and Output >> R Series >> Basic IO >> Analog Input - R Series".
The thing is, it works.. mostly.. I manage to send in a sine wave, and see it. However, every now and then, when I set teh Waveform Graph X-axis to autoscale, and change the Update Mode, every time I put it into mode Scope Chart, it freezes my computer, and I have to physically power off my computer and power it back up (which i'm not happy about). I'm using the default settings for the example, my card is in RSE mode, input signal at 25 Hz, 4V p-p
I doubt anyone can guess why this is happening, but is there any way to file a bug report?
Thanks,
Hardware: Quad-core Xeon 2.33 Ghz, 8 GB RAM, PXI-7583R FPGA, PXI-1036 Chassis
Software: Labview 8.6.1, LAbview FPGA 8.6., Vista 64-bit
NI Hardware: PXI-7853R, PCI-5122, PCI-6733, PXI-1036, PCI-MIO-16E-4, PCI-6110
Computer Hardware: Xeon Quad Core - 2.33 Ghz, 8 GB RAM
Software: Labview 2009, Labview FPGA 2009, Vista 64-bit, MAX 4.6, DAQmx 9.0, NI-SCOPE 3.5

1... Adding an unrelated question to a 3-month old post is not the best way to get your questions answered.
Start your own thread next time.
2... The example works fine for me. The EQUALS function works just fine for strings. Be aware of some things, though:
Case matters. If you want to ignore case, then uppercase both strings (or lowercase them) before comparing.
Length matters "X" is not the same as "X ". "123" is not the same as "1234".
Steve Bird
Culverson Software - Elegant software that is a pleasure to use.
Culverson.com
Blog for (mostly LabVIEW) programmers: Tips And Tricks

LabView fpga VHDL code and compiler

Hello,
I'm in the project where we would like to use NI hardware (more likely cRIO system). With NI hardware we will read/wright several AI/AO and DIO and perform some math and controls on the result of readings. We are planning to design FPGA code for project, but we are thinking about implement all data processing and control logic in VHDL and link it with AI, AO and DIO with help CLIP or IP Integration Node as explained in this : "white-paper": http://www.ni.com/white-paper/7444/en/
Mentioned above paper explain how to implement VHDL code in LabVIEW FPGA VI using CLIP or IP Integration Node, but the topic that is not highlight explicitly is how these construction CLIP and IP Integration Node will be handled by Compiler. The main reason for such approach (VHDL linked with part that read/write into hardware AI AO and DIO) we expect that our VHDL code will be handled by LabVIEW compiler without modification and passed to Xilinx Compiler synthesis as is (path for Compile process I've taken from here: http://www.ni.com/white-paper/9381/en/ ), so we will be able at some level bypass the intermediate process of compilation and get almost the same result as if we design pure VHDL code and use Xilinx ISE for Synthesis Mapping and Bit File generation.
Will this approach work? I was not able to find any documents that explain the Compiler behavior and confirm that VHDL code handled untouched or will modified, does such document exist?
Note. I've requested official assistance from NI support on topic above, but I would like to post this question on forum hoping get more feedback.

Hello RangerOne,
There won't be any modications to the internal logic of the VHDL that you implement in the IP integration node. Though I've seen developers unfamiliar with LabVIEW FPGA get tripped up on the synchronization registers that LabVIEW FPGA inserts into the code around the integration node. Learning where and why these syncrhonization registers are inserted has in my experience always resolved this issue. These two help documents do a good job of explaining the 'where and why' of synch registers when the enable chain is present, or when working with IO inside of a SCTL.
With regards to the stability of LabVIEW FPGA, I would second Daniel's sentiments. What about the known issues list conveys instability and risk? As a point of comparison, here are the known issues for ISE 14.x.
If you are looking to minimize risk, I would recommend developing the critical logic in the development enviroment in which you are comfortable setting up a comprehensive test bench since testing the code is the only way to truly verify its functionality. For me this would be LabVIEW FPGA as it has excellent trouble shooting tools and I've been developing in it for quite some time. Perhaps you're more familiar with ISE than LabVIEW FPGA and that is the source of your trepidation? If that is the case then you may find the High Performance FPGA Developers Guide a good read. You may also find a few of the case studies on our website reassuring since they demonstrate other teams successfully implementing a solution using LabVIEW FPGA. Here's one that used LabVIEW FPGA in conjnction with VHDL IP similiar to what you are doing.
National Instruments
FlexRIO Product Support Engineer

Split signal into XY components

Hi,
I am new to LabVIEW but have spend a huge amount of time (mainly going round in circles not getting anywhere) trying to get my VI design working. All very frustrating since I know what I want the VI to do but cannot figure out how to implement it in LabVIEW (despite hours of searching in this LabVIEW forum and in the help files).
I need to....
Take a signal from DAQ Assistant, when the signal is at a particular threshold (user configurable via Front Panel) log the data to Measurement File and stop logging when the signal reaches a higher threshold (I tried using the 'Trigger and Gate' VI in Express but it doesn't allow user configurable values for thresholds (only integers)).
Then I need to read back the Measurement File and split it into its XY parts to display on an XY Graph (and keep it displayed on the front panel for user observation).
Any help would be greatly appreciated but please explain in detail as I've already played with LabVIEW for hours and hours and haven't got anywhere.
Regards,

Hi bunnykins,
I think you can try using normal greater than /less than comparison functions and log the data using the Write to measurement file with append to file option enable.I have attached the screenshot of the block diagram.Please have a look. Thanks and regards, srikrishnaNF
Attachments:
first.png.zip ‏21 KB

Labview fpga development board

hi all
can i programme my own development board having xillinx fpga using labview fpga .. or lab view fpga can only be used by national instruments hardware ?
Regards

Just to reiterate what was already said, The LabVIEW FPGA generates VHDL code that can not be used or downloaded into non-NI hardware, even if it uses the same Xilinx FPGA.
That being said, there is one board that you can use that is not National Instruments, Xilinx SPARTAN-3E XUP Starter Kit
Regards,
Andrew Eddleman
National Instruments
RIO Embedded Hardware PSE
CompactRIO Developers Guide

Labview FPGA encoder reading

hello,
I an new in LabVIEW FPGA programing so I would appreciate any help. I am using sb-rio 9636 card and optocoupler for speed messaurment of DC motor. I have conected everyting right and the sensor is giving me date. But messauring the speed the oscilations of sensor data are huge. I am not changing the speed and motor continiousliy is rotating in the same speed but data are not the same. For example im 12 V that is the max speed motor schould rotate in 6500 rpm/min but in one second it is showing 6500 and in the other 5500 rpm/min. think that there is not problem in the code but that the messaurment are not reliable. I will put my code. I need to know is there anz other way to do encoder readings.
Thank you

I don't see anything in your loop that guarantees the timing of your sampling of the digital encoder pulses. It appears you expect that loop to run at 1MHz based on the uS unit label on your time of flight indicator.
Because you are using front panel indicators for some of your calculation variables, I can't see all the numbers going into your calculations.
How much variance do you see in the time of flight measurement on your front panel? You must remember that you are making measurements in whole integers of uS. How much change in the RPM calculation do you see if the uS measurement drifts by 1 uS?
If the impact of 1uS change in pulse to pulse measurement has a big impact on your calculation, then you will need to adjust your algorithm to get a more precise measure of the time of flight.
Some ideas:
The faster your sampling loop runs, the more likely you will sample the signal right after the pulse transistion. Consider using a Single-Cycle Timed Loop to sample at speeds in the 40MHz (25ns period) range. This will give you more precision. One risk I can't rule out in your existing code is that you may be sampling slow enough that in some cases you miss a pulse completely. If you want to ensure that you do not miss any pulse edged, then you must ensure that the loop is sampling at least 2x the frequency of your pulse train, assuming the pulses have a clean 50% duty cycle. If that duty cycle is not 50%, then the maximum sampling period must be shorter than the shortest pulse you expect.
Rather than measuring the time difference from pulse to pulse, measure the time of 10 pulses, or 1000 pulses, or some other larger number. This averages a larger number of pulses so that the difference of 1us resolution has less impact on the calculated measurement.

Labview FPGA: Why not have local variable without indicator?

In Labview FPGA, to transfer data among parallel loops, there are three ways or maybe more, local variable, global variable and block memory. The problem with local variable is that it needs an indicator along with, not like global variable. I was thinking why Labview doesn't make a kind of local variable not need indicator? I guess local variable itself doesn't cost resource much compared to global variable, however when it comes into indicator, it will cost more. Just an idea, though. I guess there is a reason NI doesn't do that.

As in Labview document, global variable can be used for transfer data among VIs, which local variable isn't capable of.
Global variable is not always a better solution. From my experience, it is still unclear among different compilations using local vs global in terms of resources. A thread here http://forums.ni.com/t5/LabVIEW/FPGA-global-variables-vs-front-panel-items/td-p/1407282 talks about that too.
Stephen, is there any documents say that global makes timing worse? I didn't see this noticeable.

LabVIEW FPGA Sine Wave Generator Reset Input Behavior

I would like to know what the output from the Sine Wave Generator express VI is while the reset input is true, and what happens to the output immediately after the reset input is set false.
I need to generate a regular sequence of positive half-cycles of a sine wave, with an arbitrary delay between them that is not related to the actual frequency of the sine wave. So my plan is basically to periodically fire a trigger in the fpga software that resets a sine wave generator and directs its output to an analog output until the sine wave goes negative, at which point the analog output is set to 0 until the next trigger.
Thanks

Muchas gracias por responder steve.bm
El problema que tengo es el siguiente, estoy desarrollando un proyecto en el cual uso los conversores DAC y ADC de la tarjeta FPGA Spartan 3E para lo cual use como base el proyecto que esta subido por la NI que se encuentra en uno de los enlaces que me dejaste,( Lesson 8 - Linking Existing VHDL Code from WebPACK into LabVIEW FPGA) del mismo solo modifique para usar el ADC y el DAC mediante el cual adquiero una señal senosoidal y la tengo que reconstruir, el problema es que como uso un generador de señal de laboratorio al ingresar la frecuencia de muestreo para obtener una buena reconstruccion, la frecuencia se baja lo cual en el proyecto real no podra pasar ya que la frecuencia ya en proyecto final la adquiero de la red electrica publica pero ahora para pruebas estoy con un generador, la verdad no se que pasa porque tiene un retrazo la señal.....
Te parece si te puedo dejar mi proyecto subido en enlace para que lo revices ??

"LabVIEW FPGA: The compilation failed due to timing violations, but there is no path information because the timing violations are not of type PERIOD

The compilation of my labview fpga vi fails with the error message "LabVIEW FPGA: The compilation failed due to timing violations, but there is no path information because the timing violations are not of type PERIOD".
In the 'final timing (place and route)' report, the requested frequencies are all below the maximum frequencies and the compilation error message is only displayed at the very end on the 'summary' page.
I tried to optimize my labview fpga vi with pipelining, but had no success.
Can anybody offer some advice on how to debug fpga code with this error? Is this really a timing error or something else?
Software:
Labview 2011, fpga 2011, xilinx tools 12.4 sp1
Hardware:
NI PXIe-1071 Chassis
NI PXIe-8108 Embedded controller
NI PXIe-7965R FPGA FlexRIO FPGA module
NI 5761 250 MS/s 14 bit Analog input digitizer
The Xilinx log of the compilation run is attached.
Also, this issue was already discussed in this thread ~6 months ago, but no satisfying answer was offered so far...
Thanks,
Fabrizio
Attachments:
xilinxlogc.txt ‏2313 KB

Hi Kyle,
the problem is: I have one computer which compiles the VI successfully and a second one which shows that error. Both use the same software setup (LV2011SP1+RT+FPGA from DS2012-01). Both use the same project file - atleast SVN shows no difference.
- You can have one FPGA VI where one computer is compiling successful and a second one complains. (Btw. I have a SRQ running in Germany on this topic.)
- More problems: After successful compiling on first computer and transferring all to second computer (using SVN, including the full project folder with all files like bitfiles, lvproj, and everything) the second computer is unable to start the RT executable due to error "FPGA VI needs to recompile". Solution so far: Call the FPGA-OpenReference with the bitfile instead of the VI (as I used to do until now)...
- More problems: After modifying the FPGA-OpenReference to use the bitfile (on the 2nd computer) and transferring all the files back to the 1st computer (using SVN as before, including the whole project) the 1st computer complains: FPGA-OpenReference is creating a different reference than is used in the VI. So what happens here? On one computer my VI is ok, the reference is typed correctly. Transferring all the files to a different computer the VI isn't ok anymore due to changes of the reference??? You know: all files are the same: lvproj, FPGA bitfile didn't change, cRIO reference didn't change...
All those problems didn't occur on my RT-FPGA projects in LV2010SP1. I'm not pleased...
Best regards,
GerdW
CLAD, using 2009SP1 + LV2011SP1 + LV2014SP1 on WinXP+Win7+cRIO
Kudos are welcome

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