Fpga compilation

Hi!
How can I compile some code to FPGA without hardware. I only want to see something about BRAMs on my FPGA. If I compile some code to FPGA with real hardware, it takes too long.
Best regards,
Solved!
Go to Solution.

HITMANNN wrote:
If I compile some code to FPGA with real hardware, it takes too long.
As long as you have defined your specific hardware in the LabVIEW project, you can compile your FPGA VIs with or without it connected, but in all cases it will take the same time to compile. Compiling to FPGA can be a lengthy process!
Thoric (CLA, CLED, CTD and LabVIEW Champion)

Similar Messages

Fpga compilation xilinx error 'Process "Map" failed' - 'unroutable situation'

When I try to compile a Labview fpga project on our new system, it fails with the following error summary (the full Xilinx log is attached):
LabVIEW FPGA: The compilation failed due to a xilinx error.
Details:
ERROR:LIT:536 - IBUF symbol "aUserGpio<1>_IBUF" (output
signal=aUserGpio<1>_IBUF) has the attribute IOBDELAY set to value NONE and it
is driving an IODELAY. If the IOBDELAY attribute is on the driving PAD, it
has precedence over the IBUF one. Either the constraint or the design need
modification to prevent an unroutable situation.
Errors found during logical drc.
Design Summary
Number of errors : 1
Number of warnings : 349
Process "Map" failed
Start Time: 10:31:49 AM
End Time: 10:55:32 AM
Total Time: 00:23:43
Hardware:
NI PXIe-1071 Chassis
NI PXIe-8108 Embedded controller
NI PXIe-7965R FPGA FlexRIO FPGA module
NI 5761 250 MS/s 14 bit Analog input digitizer
Installed software:
Labview 2011 version 11.0
Labview FPGA module 11.0.0
FPGA compilation tools (Xilinx12_4)
NI FlexRIO Adapter Module Support 2.2.0
NI-RIO 4.0 (FlexRIO 2.1.0)
Xilinx DRAM compilation bug fix patch from NI article id 5E4FNCDP
Xilinx clock bug fix patch from NI article id 5GFAB7DP
replaces c:\NIFPGA\programs\Xilinx11_5\ISE\xilinx\lib\nt\libPlXil_Clocks.dll; The installed version is c:\NIFPGA\programs\Xilinx12_4-> Manually copied the dll to the installed version
The Project uses the 5761 low speed clip and a DRAM FIFO.
I tried to compile it before installing any patch, after installing the DRAM patch, and after installing both patches and always got a Xilinx error after ~10 minutes compile time. The error summary shown above and the attached Xilinx log are from compiling with both patches installed.
It compiled correctly on our older system:
Hardware:
NI PXIe-1082 Chassis
NI PXIe-8133 Embedded controller
NI PXIe-7965R FPGA FlexRIO FPGA module
NI 5761 250 MS/s 14 bit Analog input digitizer
Installed software:
Labview2011version10.0.0
LabviewFPGAmodule10.0.0
FPGAcompilationtools (Xilinx11_5)
NIFlexRIOAdapterModuleSupport2.1.0
NI-RIO3.5.1 (FlexRIO1.5.0)
XilinxDRAMcompilationbugfixpatchfromNIarticleid5E4FNCDP
Any help / suggestions greatly appreciated,
Fabrizio
Attachments:
XilinxLog.txt ‏1482 KB

Hi Torpedotown,
Can you tell me what version of FlexRIO Adapter Module Support you are using?
The 5761 Low Speed CLIP has a constraint that doesn't work properly with some versions of the compilation tools. In order to solve this you should be able to upgrade to our latest version of FAM support, or go change the constraint manually.
For the latest version of FAM support, go to http://ni.com/info and enter code "famsoftware"
If you've modified constraint files before and feel comfortable doing it yourself, let me know and I can provide you with the details on how to do that.
Thanks!
National Instruments
FlexRIO & R-Series Product Support Engineer

Xilinx version availability for labview fpga compile

While trying to compile a Labview vi for target NI PXI 7831R, at first I didn't have
any Xilinx compile so I asked my network guy to instal it. Now it complains
that it needs 10.1 when 11.5 is available. I asked him to install the 10.1 and
he did but it isn't available to the NI FPGA compile worker. How do I solve
this?
thanks

Hi DonQuixote,
You are correct in that the PXI 7831R requires Xilinx Compile Tools 10.1. This is because this card has a Vertex II chip. You can read more about Xilinx requirements here: http://ae.natinst.com/public.nsf/webPreview/A4B20D58C051DFB386257A56007BB0B2?OpenDocument .
Have you uninstalled version 11.5? What version of LabVIEW do you have? Are you recieving an error or some other message? If so, please post a screenshot.
Thanks!
Dayna P.

FPGA Compiler

Hi All,
Sine Generator - R Series.lvproj is one of the examples in the Example Finder. The example is developed for PXI 7831 R Series card. But it’s mentioned that the example can run on PXI 7841 Series card also. So I created new target and devices (7841) in the PXI system and moved the Items to Move to my new target, then I run the Sine Generator (FPGA).vi but not successful. The compiler is hanging in the following window for hours.(I am using LabVIEW 2010 with xilnix 11.5 FPGA compiler)
Also I am facing the same problem when compiling the attached simple FPGA VI. This VI has only Sine Wave Generator function and I/O node.
Why I couldn't compile the attached simple VI or provided example VI. Please add your inputs/comments
Thanks in advance
Attachments:
test3.vi ‏36 KB

There's a trick here for significantly speeding up the compilation process on certain CPUs: http://forums.ni.com/t5/LabVIEW-FPGA-Idea-Exchange/Multi-core-Compiling/idc-p/2301338#M297
(It looks like your CPU is supported)
Certified LabVIEW Architect, Certified TestStand Developer
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NI Week: 2012, 2014
Knowledgeable in all things Giant Tetris and WebSockets

FPGA: compilation error: size of concat operation is different than size of the target

Today I got an error, for which I couldn't find a solution.
I use the PXI-7813R FPGA, with Xilinx tools 10.1
At compilation, the error I get is:
Compilation failed due to a Xilinx error.
Details:
ERROR:HDLParsers:804 - "C:/NIFPGA/jobs/TESY1S8_X4PR8hn/NiFpgaAG_000000ce_CaseStructureFrame_0000.vhd" Line 301. Size of concat operation is different than size of the target.
ERROR:HDLParsers:804 - "C:/NIFPGA/jobs/TESY1S8_X4PR8hn/NiFpgaAG_000000ce_CaseStructureFrame_0000.vhd" Line 372. Size of concat operation is different than size of the target.
-->
Total memory usage is 185944 kilobytes
Number of errors : 2 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
Process "Synthesis" failed
Start Time: 18:25:26
End Time: 18:28:54
Total Time: 00:03:27
What can cause a concat size difference?

This is by the way the configuration:
Project: FPGAWrapperMG100125AOD.lvproj
Target: FPGA Target (RIO0, PXI-7813R)
Build Specification: fpga_integrator_AOD_random_access
Top level VI: fpga_integrator_AOD_random_access.vi
Compiling on LabVIEW FPGA Compile Cloud Service
Compilation Tool: Xilinx 10.1
Start Time: 05.07.2011 19:06:12
Run when loaded to Fpga: FALSE
Xilinx Options
Design Strategy: Custom
Synthesis Optimization Goal: Area
Synthesis Optimization Effort: Normal
Map Overall Effort Level: Default Xilinx setting
Place and Route Overall Effort Level: High
JobId: FNW72uPWorking Directory: C:\NIFPGA\compilation\FPGAWrapperMG100_FPGATarget_fpgaintegratorAO_9D5B4237
The Xilinx log is attached.
Attachments:
XilinxLog.txt ‏80 KB

Why is the FPGA compiler server so slow?

FPGA Cloud compiler is faster because NI servers are high performance, right????
Well, my Windows 7 PC is high performance, but no luck there!
Total CPU usage is never more than 25% and total memory usage (including other applications) is less than 16%.
Why does the compile server not use all available resources? has it been restricted?
How can I leverage more power from my PC?
If NI Servers can compile code quicker, there must be plausible explanation / reason?
Please advise, how to make the compile server run faster locally?
Solved!
Go to Solution.

Try this if you haven't yet:
http://forums.ni.com/t5/LabVIEW-FPGA-Idea-Exchange/Turbo-Boost-the-speed-of-FPGA-compiles-under-Wind...
In my experience, taking advantage of Intel's Turbo Boost (my PC has i5) reduced compile time from 85 minutes to 45.
I'm currently testing Cloud Compiler and it took 110 minutes. How can Cloud Compile Server be the slowest compile?

PC Configuration for Fast LV FPGA Compile

What's the state-of-the-art PC for fast LV FPGA compile?
My life becomes short, when I have to wait 2 hours to compile a 90% usage 5640R VI on my Dell Dimension 2.8GHz PC. I toggled the hyper-threading on and off, it does not change too much.

The Xilinx tools do not make use of multiple processors so having hyperthreading or multiprocessor systems will not help compile faster. Although it will allow you to work on other things using the available processor while the compilation of the FPGA consumes the other processor. The best thing to have for your system is a lot of RAM. According to Xilinx you should have between 1-2 GB for the FPGA device in the PCI-5640R.
Regards,
Joseph D.

FPGA compilation not completing.- Generating Cores

When i compile my FPGA code I get the above window and will be in the same status for more than 10 hrs and still no progress and no errors are thrown by the compiler. I have tried with different Design strategy like Balanced, minimum time etc

What version of LV? OS?
Has FPGA compilation ever worked on this computer?
For test purposes, have you tried compiling a very simple FPGA VI? Does this happen with any VI you try to compile?
Can you tell by looking at the task monitor whether the compiler is still actively doing something (consuming CPU cycles) after 10 hours?
Mike...
Certified Professional Instructor
Certified LabVIEW Architect
LabVIEW Champion
"... after all, He's not a tame lion..."
Be thinking ahead and mark your dance card for NI Week 2015 now: TS 6139 - Object Oriented First Steps

How can I reduce FPGA compiler time

Hi,
I am trying to implement a PID control loop on the FPGA of a cRIO.
The VI which runs on the FPGA target takes very long to compile (1h+).
Does anyone have an idea while the compilation takes so long and how I might be able to inprove compilation time?
The program can be found in attachment.
Best regards,
Jasper
Attachments:
PID FPGA TEST.zip ‏160 KB

Hi Jasper,
FPGA's normally take a very long time to compile compared to software compilations. 1 hour sounds about right for a slightly above average sized project. Compile times of anywhere from 2-4 hours (and longer for larger devices!) are not unheard of.
Companies who are serious about FPGA compilation and rely on quick turnaround invest in servers which contain many computers to work on the compilation (this is also why when you compile, it asks you if you would like to compile on the "local sever" (your computer) or an external server).
NI also has a cloud compiler available that will let you compile your code on their servers, however you must pay for the time. I think they offer a free trial if you wanted to see how it works.
So if you seriously need quick turnaround, you must consider some serious hardware.
Otherwise, you will have to queue up multiple compilations and let them run overnight like the rest of us.
www.movimed.com - Custom Imaging Solutions

FPGA Compile Error due to error in mapping process

Received the following error while trying to compile a FPGA VI on a PC. (Refer to attachment for details). My PC has a fresh installation of English Windows 2000 with sp4. No other software is installed except LabVIEW 8.2 & FPGA Module 8.2 & NI-RIO.
I have checked this KB and confirmed that regional settings are English. But the error still exists. I tried compiling the same VI on my laptop with Windows 2000 sp4 and it was successful. Can someone help me? Thank you very much!
FPGA Compile Error When Compiling LabVIEW FPGA VI
Error found in mapping process, exiting...
Errors found during the mapping phase. Please see map report file for more
details. Output files will not be written.
Design Summary
Number of errors : 17
Number of warnings : 8
ERROR:Xflow - Program map returned error code 2. Aborting flow execution...
Message Edited by maimai on 01-08-2007 01:00 AM
Attachments:
FPGA Compile Error.txt ‏8 KB

Hello,
The key will of course be to isolate differences between your machines.
I wonder if the following more specific language setting could be the lingering problem. LabVIEW is a non-unicode program, and there is a language setting in Windows (at least XP) specifically for non-unicode programs. Try the following (or it's Win2K equivalent) if you haven't already:
0. Open "Control Panel"
1. Open the "Regional and Language Options"
2. On the Advanced tab, choose English (United States) from the drop-down menu under the top section "Language for non-Unicode Programs"
- This language setting is different from the setting on the "Regional Options" tab.
Any other differences you can isolate would be potentially insightful - if you have the same software versions installed in the same order on both machines, we may be looking for something a bit subtle, such as the suspected language setting.
Best Regards,
JLS
Best,
JLS
Sixclear

Has anyone used the fpga compile farm toolkit?

Hello all,
This is my very first post, I have been trolling these forums for about two months now. I hope this is an okay board to post this question too.
My question is if anyone has any experience using the cFPGA compile farm utility, and if it is worth the expense? The team I work for is getting ready to re-write a mojor peice of software that will be used on 15 C-Rios for a whole bunch of hardware control and data aquisition. Needles to say we will be doing a fair ammount of compiling and we dont want to tie down our work machines with these tasks, and instead would like to have some older desktops grind it out.
Thank you so much for any feedback you can give.

Hi Unavailable
As I am an Application Engineer and I work for National Instruments, I would like to make an I impartial advice, I will highly recommend you to install the FPGA compile farm toolkit on a computer and use it as evaluation software, that way you could try it yourself and have your own opinion of the toolkit.
I think that if you will have to run many compilations it might be a good inversion. But as I told you above it will be better to try it and decide for yourself.
Regards
Esteban R.

Unable to connect to the fpga compile server

Hi, I keep getting the following message when trying to compile my FPGA code -> LabVIEW FPGA was unable to connect to the FPGA compile server.... System configuration: Win 7 64LV 2009 (32 bit) SP1LV FPGA 2009 SP1cRIO 90249114 Chassis I am developing and compiling on the same machine with the cRIO attached through a wired router. I've tried repairing the FPGA installation with no changes. The attached screen shots are displayed in the order they are pasted Any insight would be appreciated - thanks in advance!

I appear to be having similar difficulties with compiling a FPGA VI remotely with LabVIEW 2010.
The remote compilation server is a PC running XP 64 bit. I have configured the compilation worker to allow remote connections and it lists it registered capabilities as Xilinx 10.1, Xilinix 11.5 and Xilinx 11.5 (64-bit). This can be seen in the attached png.
My development system is running XP 32 bit with LabVIEW 2010. It is connected to the server via a local area network.
The process I have been following is as follows;
1.) Log onto the server PC and start the compile worker (this is either physically or by connecting via remote desktop and then disconnecting but leaving the PC logged in with compile worker on)
2.) Set up the FPGA compilation settings on the development computer to be the server (hostname, domain\username, password)
3.) Try and rebuild the target VI
I then receive an error stating that the user name is too long or invalid (see png).
I have set the exceptions in the server firewall to allow port 96 as I found that this is the default port used for earlier version of the compile server but I am unsure if this is applicable in 2010. I need to check with my IT services that exceptions I add are actually applied.
If I go into the compile worker settings on my development PC and try and set them to that of the compile server then it also fails to connect.

Is it true that bundle by name can cause FPGA compiles to fail?

Dear forum,
I have attached a full log of my experience with this apparent bug, but I will summarize it here:
I attempted to compile a labview robotics project for cRIO 9074. The code was all on the FPGA, and I'd tested it all before attempting to compile--much of it was skeleton code proving that the self test system would turn on blinky lights on the front panel. My first attempted compile received a strange failure message in stage 3 of labview's pre-xilinx compilation interface, and the message was strange mostly because it was so intensely vague. It read "An internal software error has occurred. Please contact National Instruments technical support at ni.com/support with the following information: Error 1000 occurred at an unidentified location. Possible reason(s): LabVIEW: The VI is not in a state compatible with this operation."
It being Tuesday the 6th of July 2010, I was unable to reach either the support staff who were on holiday or the web service, which was down for maintenance, so I began disabling pieces of my code using my debugging conditional disable statements. Eventually I found one skeletal code module, one to interface with analog flood sensors, which did not fail to compile. I compared this with another skeletal code module which did fail to compile, and after several tests noticed that adding a bundle by name from a strict type definition (but not an un-bundle by name or a standard anonymous bundle) would cause the vi to fail the compile. With several more tests I confirmed that while the vi would fail to compile with the bbn, with a standard bundle it would compile successfully all the way to the xilinx stage (by which point I didn't care, the bug was definitively pre-xilinx.)
So tonight I will be going into my code and doing a lot of replacing bundle by name blocks with anonymous bundles, but I am still haunted by the extreme vagueness of the error, and by the fact that bundle by name is usually a solid part of the FPGA development platform. It was clearly intended to work. Why didn't it?
Gray Cortright Thomas
Franklin W. Olin College of Engineering
Engineering: Robotics
Class of 2012
Needham, MA
Gray Cortright Thomas
Franklin W. Olin College of Engineering
Engineering: Robotics
Class of 2012
Needham, MA
Attachments:
gtlog2010-07-06-18-24-00.txt ‏7 KB

So I did as Donovan suggested, and this worked for the code example which I posted. But when I started trying to put more of the bundle by names back in this solution stopped working. I then went on to solve a seemingly unrelated problem with the version that had compiled using only anonymous bundle: it had been unable to run some while loops that were in subvis. When I took the code from these subvis and put the loops on the back panel of the main vi, to my utter horror, they began to function again in the compile (running on the hardware). I was afraid that it was subvis themselves that were causing this failure to run, but was relieved when my next test proved this not to be the case: I took that loop on the front panel where it worked and used edit>create subvi to put it in a subvi. It still worked. Thus I was left to search out the difference between the subvi that successfully compiled, and the subvi which compiled but didn't run--and this was that the failed subvi was part of a library. I placed the new, working, subvi in the same library and the code once again displayed the same symptoms as when it had been tested the first time: the loop would not run even once and the flow of control would never finish with the loop--it just delayed forever. This might be a problem with the way I had used the libraries, but I think everything within them was public. My guess now it that the Libraries don't behave the same way they do on the FPGA as they do on the FPGA simulator, and this is why the vis seemed to work when I simulated them. So... I took all the vis, typedefs, and globals out of the libraries and into virtual folders of the same name and... Everything works! Even bundle by name!
The implementation of project libraries in the FPGA compiler may be suboptimal in some respects, but I probed only as deep as necessary to run my code.
And this code is in 7z format because my zip file did not meet the maximum file size requirements of the forum.
It is also very possible that I misunderstood the functioning of the libraries, and the FPGA simulator was blowing sunshine up my nose when it showed them working properly in simulation. Either way, it is probably worth looking into. This weekend I might try to find the simplest project file that shows these symptoms just to prove I'm not crazy.
Gray Cortright Thomas
Franklin W. Olin College of Engineering
Engineering: Robotics
Class of 2012
Needham, MA

Fpga compilation extremly slow

Hey guys,
Im hoping Im right here. My problem is that when I try to compile my fpga VI, Xilinx 14.4 needs more than 9 hours to compile.
One example is that the program needs for this:
"INFO: [Designutils 20-295] Found reset/set on shift register ending at window/theVI/n_bushold/Clk40Crossing.Clk40ToInterface/BlkOut.SyncIReset/c1ResetFromClk2. Adding 1 LUTs and 3 Flops to estimation."
a few minutes. I think there are thousends of that messages in the log. Why do the compilation need so much time?
My System:
Intel Core i5-3337U CPU @1,8 Ghz
4GB Ram
I have a SSD with round about 30 GB left. I think you need more informations. Please tell me what else do you must know that you can help me.
Thank you

When your FPGA compilation completes, what % of resources does it use on the FPGA (i.e. are you close to filling it)? What device are you compiling for? How complex is your FPGA VI and what sort of functionality does it perform? (FIFOs, complex math?)
I know there are certain conditions that can make routing the FPGA very difficult for the compiler (trying to route lots of signals to physical pins that are far apart) or you might be using operations that make the code very inefficient (such as doing lots of divisions, handling arrays or floating point arithmetic).
I don't expect it to make a lot of difference, but on your FPGA build specification settings (Xilinx Options) are you optimising for compilation speed or resources?
As is normally the case - if you could post your VI it may help to identify the cause of the issue. The error seems to be related to a shift register but without seeing what you're trying to do with it it's difficult to assist.
Certified LabVIEW Architect, Certified TestStand Developer
NI Days (and A&DF): 2010, 2011, 2013, 2014
NI Week: 2012, 2014
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FPGA compiler Server status says idle but Status says compiling VHDL

when i compile my FGPA vi file , after some time in the compile server window "Server status" shows "idle.." but the status box shows "Compiling VHDL".
It stays in this condition for a long time about 30 mins. Why is this happening? I am also attaching the screenshot of the compile server.
FPGA vi i am trying to compile is the Sine Generator.vi which was there in examples under FPGA Fundamanetals->Analysis and Controls.
Attachments:
compile server.JPG ‏59 KB

I am attaching the block diagram of the fpga vi. It is a sine generator example which was in the labview examples folder.
I am seeign this behaviour only when i compile this fpga vi. I have compiled other fpga vi's without any problem.
Attachments:
fpga vi for sine genrator.JPG ‏127 KB

FPGA compile error

Good Afternoon,
I am getting a compile server error that I do not know how to track down. The server is set up and working fine (LV 8.6 cRIO, FPGA) I can send over on FPGA file and it compiles fine. When the second is sent, the compile request is received and starts, but a quickly get the following pop-up:
"Status: Compilation failed due to a Compile Server error.
Regenerating IP...
ERROR:coreutil - Failure to set parameters on core: Illegal combination: Port A
   Width and Port A Depth
ERROR:coreutil - Failure to generate output products
ERROR:coreutil - An error occurred while running Java. Please examine the
   console or coregen log file for a specific IP related error.
   If there is no specific error the problem may be due to memory limitations.
   For more information please consult solution record 21955 available from:
   http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=21955Finished Regenerating.
ERROR:sim:57 - Error found during generation
Start Time: 2/17/2009 10:22:28 PM
End Time: 2/17/2009 10:22:54 PM"
I am aware that something is amiss in my FPGA VI, but I am unsure what the above messages are telling me to look at. Any ideas? It was working/compiling, but I changed the cRIO backplane configuration, removing some inputs and adding different ones.
Message Edited by Mellobuck on 02-17-2009 09:51 AM
Data Science Automation
CTA, CLA, CPI
SHAZAM!
Solved!
Go to Solution.
Attachments:
FPGA error.JPG ‏63 KB

Xilinx doesn't support a depth of 1. If possible
carry on using a depth of 8 or use some other "register" to hold the
value such as locals, globals, fifos, feedback nodes, etc. Have a look at the following:
Why Won't FPGA Code with a Memory Depth of 1 Compile?
Adnan Zafar
Certified LabVIEW Architect
Coleman Technologies

Fpga compilation

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