NI 9234 : sampling rate : cRIO, FPGA

For NI 9234 module, front panel and block diagram of my FPGA code of my cRIO is like below.
The sampling rate (data rate) is selectable between some values as shown below.
Do you have any idea how I can do the sampling with a lower rate that is smaller than the samllest option (1.652 KS/s)?
Solved!
Go to Solution.

Hi Cashany,
Take a look at this link. Page 16 describes the limitation that you are running into. Basically the master time base can only be divided down to certain data rates because of the way the device physically handles digital and analog filitering. So there really isn't a way to divide down past that point.
Ryan
Applications Engineer
National Instruments

Similar Messages

How to set accurate sampling rate in FPGA programming.

Hi all,
I'm using cRIO 9004 and NI 9233 for acquiring high speed analog inputs. Module 9233 specify some data rate values which can be programmed. I want to acquire data without missing a single sample. please comment on this.

Couple things to add to what Mike said:
For C Series modules like the NI 9233 when used on the CompactRIO platform, all configuration and programming is done from within LabVIEW.
To configure the data rate at which the 9233 will acquire data, you need to either get into the module's properties page (in LabVIEW) and set it there, or you programmatically do it by using a LV FPGA property node on the module. I suggest you look at the examples that ship with CompactRIO for the 9233.
JMota

CRio FPGA read 1024000 samples and transfer to RT

Hello,
I have a cRIO application and i have to read 1024000 samples, on 3 channels at a sampling rate of 25.6 khz.. My NI 9232 offers the posibility of sampling at such a rate. The problem is that i do not know how to aquire and transfer that amount of data to the RT. I'd be grateful if someone could help me.
Attachments:
FPGA.vi ‏60 KB
RT.vi ‏359 KB

Valentina,
You are correct to mention that your data will not be continuous with the abort node. I only mentioned that you should use the abort node because your FPGA VI was not sampling continuously and you were restarting the FPGA from the RT target.
If I understand your application correctly, you’d like to continuously analyze a set of 1024000 samples on the RT target. Is this correct?
If so, why are using a For Loop to read from the AI node only N times (where N = Samples per Channel)? Why not place the AI node and FIFO Write method in a while loop, as done in the Streaming Data (DMA).lvproj example, which you can find in the LabVIEW Example Finder? By placing these nodes in a while loop, you’ll get a continuous stream of data from the FPGA until you tell the while loop to stop.
On the RT side, you can also use a while loop to continuously read the data in the FIFO. If reading 1024000 samples from the FIFO at once does not work for you, you should consider setting the number of elements to read from the FIFO to a value where 1024000 is a multiple of it. This approach might take a little more work because you have to join N iterations of the FIFO data together in order to pass a set of 1024000 samples to your analysis function.
Regards,
Tunde S.
Applications Engineer
National Instruments

How to build a array with high sampling rates 1K

Hi All:
Now I am trying to develop a project with CRio.
But I am not sure how to build a array with high sampling rates signal, like >1K. (Sigle-point data)
Before, I would like to use "Build Arrary" and "Shift Register" to build a arrary, but I found it is not working for high sampling rates.
Is there anyother good way to build a data arrary for high sampling rates??
Thanks
Attachments:
Building_Array_high_rates.JPG ‏120 KB

Can't give a sample of the FPGA right now but here is a sample bit of RT code I recently used. I am acquiring data at 51,200 samples every second. I put the data in a FIFO on the FPGA side, then I read from that FIFO on the RT side and insert the data into a pre-initialized array using "Replace Array subset" NOT "Insert into array". I keep a count of the data I have read/inserted, and once I am at 51,200 samples, I know I have 1 full second of data. At this point, I add it to a queue which sends it to another loop to be processed. Also, I don't use the new index terminal in my subVI because I know I am always adding 6400 elements so I can just multiply my counter by 6400, but if you use the method described further down below , you will want to use the "new index" to return a value because you may not always read the same number of elements using that method.
The reason I use a timeout of 0 and a wait until next ms multiple is because if you use a timeout wired to the FIFO read node, it spins a loop in the background that polls for data, which rails your processor. Depending on what type of acquisition you are doing, you can also use the method of reading 0 elements, then using the "elements remaining" variable, to wire up another node as is shown below. This was not an option for me because of my programs architecture and needing chunks of 1 second data. Had I used this method it would have overcomplicated things if I read more elements then I had available in my 51,200 buffer.
Let me knwo if you have more qeustions
CLA, LabVIEW Versions 2010-2013
Attachments:
RT.PNG ‏36 KB
FIFO read.PNG ‏4 KB

PXI-7831R analog input max sampling rate?

I'm using 5 of the analog inputs on the 7831R and seem to only be able to get a max sampling rate of 10K per channel. Looking at the specs it should do at least 10 times this per channel, also the time for the A/D loop is 228 ticks of the 40MHz clock so this would suggest a higher sampling rate than just 10K. I'm missing something here... Any ideas as to what the deal is?
pete

Hi Pete,
You are right in saying that the 7831R boards should acquire data much faster than 10KHz. Infact you can take a look at the actual specs from the data sheet http://sine.ni.com/nips/cds/view/p/lang/en/nid/14757 as well as the product manual. However, I am concerned that you may be measuring the rate of acquisition on the RT VI (or any host vi) you are running as opposed measuring it in the FPGA VI.
Your time critical loop may be running at 228 ticks of the 40 MHz clock but the data is buffered (at that rate) and has to be then transferred to the communication loop which then sends the data to the host vi (which may be your RT vi). Hence, the rate at which host VI receives the data will be much slower than the FPGA VI is acquiring data.
Hope this helps!
Prashanth

How to improve sampling rates in mega samples spartan 3e board

I am trying to acquire data in spartan 3e board in mega samples rate can you post me any examples for this purpose
Solved!
Go to Solution.

If you're trying to get analog samples in that range, the issue that you're going to run into is that that sort of sampling rate is right at the bleeding edge of what you're asking for (it's a 2-channel @ 1.5Msps chip, the LTC1407A-1). If you actually want to capture at these rates, you're going to need to pull some interesting LV-foo using single-cycle timed loops in the FPGA diagram or drop some code down into an IPNode/CLIP Node, with outputs from those IP blocks hooked to the IO in a SCTL.
Please let us know a bit more about your specific design.
-Brad

[cRIO] FPGA compile time

Hello, I was wondering the normal time for LabVIEW to compile a program for cRIO FPGA target.
It has been taking 15 minutes per compile. I was wondering whether this is normal or whether there
is something I could do to make it faster.
- Thank you

This is the compile report of the code I am working with:
Status: Compilation successful.
Compilation Summary
Logic Utilization:
Number of Slice Flip Flops:       5,531 out of 40,960   13%
Number of 4 input LUTs:           5,475 out of 40,960   13%
Device Utilization Summary:
   Number of BUFGMUXs                        2 out of 8      25%
      Number of LOCed BUFGMUXs               1 out of 2      50%
   Number of External IOBs                 164 out of 333    49%
      Number of LOCed IOBs                 164 out of 164   100%
   Number of MULT18X18s                     14 out of 40     35%
   Number of Slices                       3874 out of 20480 18%
      Number of SLICEMs                      4 out of 10240   1%
Clock Rates: (Requested rates are adjusted for jitter and accuracy)
Base clock: 40 MHz Onboard Clock
      Requested Rate:      40.408938MHz
      Theoretical Maximum: 54.191730MHz
Base clock: MiteClk (Used by non-diagram components)
      Requested Rate:      33.037101MHz
      Theoretical Maximum: 61.406202MHz
Start Time: 9/18/2008 12:13:18 PM
End Time: 9/18/2008 12:29:22 PM
This is the compile report if I delete most of the code.
It only has a while loop and I/O pin read and write, and an inverter.
[Screenshot]
Status: Compilation successful.
Compilation Summary
Logic Utilization:
Number of Slice Flip Flops:         583 out of 40,960    1%
Number of 4 input LUTs:           1,021 out of 40,960    2%
Device Utilization Summary:
   Number of BUFGMUXs                        2 out of 8      25%
      Number of LOCed BUFGMUXs               1 out of 2      50%
   Number of External IOBs                 164 out of 333    49%
      Number of LOCed IOBs                 164 out of 164   100%
   Number of Slices                        671 out of 20480   3%
      Number of SLICEMs                      4 out of 10240   1%
Clock Rates: (Requested rates are adjusted for jitter and accuracy)
Base clock: 40 MHz Onboard Clock
      Requested Rate:      40.408938MHz
      Theoretical Maximum: 85.113627MHz
Base clock: MiteClk (Used by non-diagram components)
      Requested Rate:      33.037101MHz
      Theoretical Maximum: 70.566650MHz
Start Time: 9/18/2008 2:00:03 PM
End Time: 9/18/2008 2:12:19 PM

I need to increase the sample rate to 50KHz to allow for arc detection

In an effort to get our arc detection software running we need to
capture data with a sampling rate greater than 10kHz. Would setting the 'samples per cycle'
to 512 (as opposed to 192) would allow us to use your re-sampled data at the
RT-Controller (permitting us to use the FPGA VI un-altered) at a sample rate greater than 50KHz?

The number of samples per cycle can be specified from 128 to 512 without having to recompiling the FPGA VI. But even with 512 samples per cycle, the sampling rate after resampling is about 512*50 or 512*60, still less than 50k Hz.
Could that meet your arc detection requirement?

Decrease NI 5791 ADC/DAC sample rate

Hello all, I am using NI 5791 and want to decrease the ADC/DAC sampling rate from 130MHz to a lower rate. I am a little confused about whether it is possible, since the manual says the ADC/DAC works "AT" 130MHz, but it also says the clock distribution IC AD9511 is programmable. So if the output (ADC/DAC sample clock) of AD9511 is programmable, doesn't that mean ADC/DAC can work at any clock rate? And if it can, how to program the AD9511 (I searched online, but there is no clue at all)?
Any help is appreciated.

Hi!
On the 5791, the only way to change the clock output from the AD9511 would be to change the clock source to use CLK IN and use an external clock. You could do this by using a Timing and Sync module (or some other clock source) to generate your new sample clock and then connect that to the CLK IN BNC connector on the front of the 5791. From there, you can select CLK IN as the clock source in LabVIEW. I would recommend taking a look at the 579X sample project that you can access by clicking "Create Project" on the LabVIEW splash screen.
If using an external clock is not an option, you will have to manually decimate your incoming IQ data on the FPGA. You could do this by only reading the data on specific iterations of your Single Cycle Timed Loop. As an example, your SCTL will be running at either IIO Module\Data Clock or IO Module\Data Clock x2. If you are using IO Module\Data Clock of 130MHz, then you will be sampling every 130MHz with no decimation. If instead, you use a case structure with an alternating boolean flag to govern when you acquire, you could read at every other iteration of IO Mod Clock, sampling at 65MHz. If you need to sample at a frequency of say 4/5 x 130MHz =108MHz, you could have some other logic to read the IO Node four out of every five iterations.
Does this help answer your question?
Rob B
FlexRIO Product Manager

NI 5761 with low sampling rate

Hi, is it possible to change the NI 5761 sampling rate without programming FPGA? Thank you very much!

Hi, as mentioned above you can play with the sample rate by using an external Sample clock. Take a look at the picture attach for the general idea. Simply replace the Boolean buttons for digital input ports. I hope this helps
Alejandro | Academic Program Engineer | National Instruments
Attachments:
Capture.JPG ‏256 KB

Audio sample rate does not match (HDcam to dvcam)

I'm trying to import clips and keep getting this message:
"The audio sample rate of one or more of your captured media files does not match the sample rate on your source tape. This may cause the video and audio of these media files to be out of sync. Make sure the audio sample rate of your capture preset matches the sample rate of your tape."
Footage was originally shot on HDCAM and transferred to DVCAM elsewhere. Using FCP 5, am importing via firewire from a Sony DSR-11 deck. Using DV NTSC 48kHz Anamorphic as capture settings (though I've tried everything that I thought might possibly work with no success). The audio does not seem to drift over the course of several 5 minute or so clips. Clip settings show audio at 48 kHz (don't know if that's from capture settings or from actual data). Seems to me all audio should be 48 kHz 16 bits, so can't figure out what's going on. I have to export an EDL for the project to be finished in HD. Read some similar threads that ended in December, seemingly without much resolution. My broader concern is why this is happening; my immediate concern is do I need to worry about this right now since the media files will need to be recaptured in HD anyway. Any thoughts?
Thanks

A little more info. I'm having this problem on 4 tapes (from different cameras) that were transferred to DVCAM in a squished format to appear full screen on a 4x3 monitor. Video that was letterboxed and I can bring in with the standard DV NTSC capture settings does not have this problem. Still have the problem if I try to import the clips from the squished video with standard settings. Any thoughts?

Sample rate off the audio input and out devices do not match - what to do?

This is fundamental, I know, but nevertheless I can't find my way around it. I get this error message when trying to recor:
Sample rate off the audio input and out devices do not match
and am asked to do this:
Use the appropriate operating system or audio device control panel to adjust the sample rates of the input and output devices to use the same settingt.
I have defined the sample rate to 44.1/16 bit in accordance with my inbuild soundcardt.
I am trying to record from LineIn.
When running on a M-Audio sound card I don't face any problems.
HP 8560W, sound card IDT/High definition audio Codec
Any suggestions?
Knud
Copenhagen

You're sure you have set BOTH the input and output settings to 44.1 16 bit?
Which version of Windows are you running? There are a number of posts on this forum about how to fully access both the Windows Mixer and the Mixer for your soundcard. Especially, you need to ensure that all "Windows Sounds" are turned OFF.

Separate sampling rate for two different channels for a USB-6009 daq

Hi,
I am using a USB-6009 and incorporating the 'daq assistant' to change the sample rate. I am trying to find a way to set the sampling rate to two unique values for two separate channels. I've tried setting up two daq assistants and adjusting the sample rate different for each channel, though this does not work. Is there any way to set the sample rate high for all channels then reduce the rate for a different channel - or an alternative? I would appreciate any input on this, thank you!
- Anthony
Solved!
Go to Solution.

All tasks on a DAQ board that use a sampling clock must use the same clock. Therefore, you cannot have two tasks on the same DAQ board sample at different rates.
Alternatives would be:
1. to combine all of the channels into a single task and just accept the extra data
2. get an extra DAQ board to use in parallel
There are only two ways to tell somebody thanks: Kudos and Marked Solutions
Unofficial Forum Rules and Guidelines

How to acquire data from 2 chs of the same DAQ card at different sampling rate

I am using single DAQ card (either 6013 or 6014) in my system i want to acquire data from 2 (or more) channels with following requirements
1. sampling rate of each channel should be independant of each other (say one is 20 Hz and other is 15 kHz)
2. data from all the channels should be acquired simultaneously.
3. coding must be done using DAQmx VIs
I have tried out following things
1. I created separate task for each channel: i found out that two tasks can not run simultaneously even though the channels are different
2. I tried out single task with two channels included in it. and i used 'channels to Read' property to determine from which ch. i want to acquire data: this method works fine if the sampling rates are same. but if i change the sampling rate of one channel it gets reflected in other channels as well.
can somebody help me out to solve this problem.
i will appreciate if somebody can post the sample code as my deadline is approaching
Tushar Jambhekar
[email protected]
Jambhekar Automation Solutions
LabVIEW Consultancy, LabVIEW Training
Rent a LabVIEW Developer, My Blog

Hi Dennis Knutson
Thanks for your suggestion.
Tushar Jambhekar
[email protected]
Jambhekar Automation Solutions
LabVIEW Consultancy, LabVIEW Training
Rent a LabVIEW Developer, My Blog

Multiple sample rate question

I have one project with edits of different files all over the place recorded at 44.1 kHz. I have another project with edits all over the place recorded at 88.2 kHz. I wish to combine all tracks from these two projects. I realize I will need to convert the sample rate of all the 88.2 kHz files, but I don't want to mix down any track. I want all of the edits to be cut at the same places in time, just with the referenced files being at a different sample rate.
I've tried everything. It seems that it is impossible. If I convert the sample rate of the referenced files, then open the project and change it's sample rate, the edits are now cut at differnt locations in time. It seems I have to mix down each 88.2 track, then sample rate convert these to 44.1.
But I need to have all the edited segments as they appear in both projects in the same project. Any ideas?

Don't record at 88.2! Why would you do that?!
I'd back up and archive your current session first as you are probably going to have to do some very destructive messing.
I haven't put this to the test but maybe you could try converting the route files in a third party software like ProTools. You'll get a bunch of prompts when you reopen Logic but this may work. But for me the simplest (albeit time consuming route) would be to convert all of your regions to new original sound files (you can do this from the audio pop down on the arrange page). Then in your audio pool select all unused audio, delete and go through each new file and convert the sample rate. It's a bit of a car crash situation needless to say next time preparation preparation preparation!
Finally when you have been through this kind of process make sure that you are operating at the correct new clock rate before continuing otherwise this stuff still aint gonna work.
Hope this is of help.
Good luck.

NI 9234 : sampling rate : cRIO, FPGA

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