Vivado HLS 2015.x config_interface -register_io

Question

Hello!
In VHLS 2015.x there is new option: config_interface -register_io. From User guide it is not clear to what types of interface this option can be applied though. Can you confirm that this option can be applied to ap_bus m_axi interface signals? If yes does this mean that AXI Register Slice core is additiobally inserted on this m_axi interface? 
I am using Virtex-7 2000t device and trying to fight timing issues in my hls core by flourplanning hls core to different SLR. HLS core has AXI master interface to AXI bus with external DDR memory. All AXI bus components including AXI Interconnect IP and DDR3 MIG core are flourplanned to SLR1 and HLS core to SLR2. I know that it is critical to register all nets that cross SLR boundary on both sides of it. I can insert AXI register slice on AXI Interconnect IP  port and I what to do the same on HLS side. 
If config_interface -register_io can not do what I want my second thought was to add one more AXI Interconnect IP on HLS side inserting AXI register slice on port that is to connect to main AXI Interconnect.
What can you suggest?  
 

Answer 1

Thanks for the reply.
Took a while to test your suggestion.
axi mmu was not enough to change the behavior of the address editor.
Still, I failed to have my AXI master interfaces capable of 64 bit addressing.
The axi master should support 64 bits for the axi_mmu to map 64bit addresses.
Though, Vivado (address editor) thinks my module has only 32bit aw_addr / ar_addr channels, even though I do have 64bit aw_addr / ar_addr channels.
Actually,
My goal was to provide a DMA64 (high memory DMA in other cases)capability to a prototype DRAM based SSD on the VC709 board.
This function was required in order to eliminate the need of bounce buffers (bouncing high memory buffers into DMA'able addresses via memcpy & stuff) in the host side.
In this case, the AXI master is my module, accessing to the axi pcie axi slave port, looking at axi2pci apertures.
I had to access axi2pci apertures which has axi addresses mapped way above 0xFFFF_FFFF (something like 0x0001_0000_0000_0000 ~ 0x0001_FFFF_FFFF_FFFF axi2pci apertures, to access host side DMA addresses such as 0x0000_0003_EC0B_0000)
During the way, I failed to address axi2pci above 32 bits even though I gave "config_interface -m axi_addr64" with my HLS module.
Eventually I managed to use the axi datamover IP, or axi cdma IP in order to achieve my goals, since the IPs were capable of addressing 64 bit axi addresses.
Though I am still wondering about 64 bit address generation in HLS.  Actually what happens when we apply "config_interface -m axi_addr64" directive. 
If it worked as I intended, I could have made AXI4 mm transactions directly from my HLS code.
Regards,
Woong.